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| m68hc08 microcontrollers freescale.com MC68HC908JG16 technical data rev. 1.1 MC68HC908JG16/d august 16, 2005
MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor 3 MC68HC908JG16 technical data freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation or guarantee regarding the suitability of its products fo r any particular pu rpose, nor does freescale assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequ ential or incidental damages. "typical" parameters which may be provided in freescale data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale product could create a situation where personal injury or death may occur. should buyer purchase or use freescale products for any such unintended or unauthorized application, buyer shall indemnify and hold free scale and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all cl aims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintend ed or unauthorized use, even if such claim alleges that freescale was negligent regarding the design or manufacture of the part. freescale, inc. is an equal opportunity/affirmative action employer. ? freescale, inc., 2002 revision history technical data MC68HC908JG16 ? rev. 1.1 4 freescale semiconductor to provide the most up-to-date info rmation, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to veri fy you have the latest information available, refer to: http://freescale.com the following revision history table summarizes cha nges contained in this document. for your conven ience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) may 2002 1 first general release. ? august 2005 1.1 updated to meet freescale identity guidelines. ? MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor list of sections 5 technical data ? MC68HC908JG16 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . . . . 29 section 2. memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 3. random-access memory (r am) . . . . . . . . . . . . . 55 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 section 5. configuration register (config) . . . . . . . . . . . . 69 section 6. central processor unit (c pu). . . . . . . . . . . . . . . . 73 section 7. oscillator (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 section 8. system integration module (sim) . . . . . . . . . . . . . 95 section 9. monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . 121 section 10. timer interface module (t im) . . . . . . . . . . . . . . 135 section 11. universal serial bus module (usb) . . . . . . . . . 159 section 12. serial communications interface module (sci). . . . . . . . . . . . . . . . . . . . . . . . . . . 205 section 13. analog-to-digital conv erter (adc) . . . . . . . . . 245 section 14. input/output (i/o) ports. . . . . . . . . . . . . . . . . . . 255 section 15. external interrupt (irq) . . . . . . . . . . . . . . . . . . . 275 section 16. keyboard in terrupt module (kbi) . . . . . . . . . . . 283 section 17. computer operating pr operly (cop) . . . . . . . . 291 section 18. low-voltage inhibit (lvi) . . . . . . . . . . . . . . . . . 297 section 19. break module (brk) . . . . . . . . . . . . . . . . . . . . . 301 section 20. electrical specifications . . . . . . . . . . . . . . . . . . 309 section 21. mechanical specifications . . . . . . . . . . . . . . . . 319 section 22. ordering information. . . . . . . . . . . . . . . . . . . . . 321 list of sections technical data MC68HC908JG16 ? rev. 1.1 6 list of sections freescale semiconductor MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor table of contents 7 technical data ? MC68HC908JG16 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 1.6.1 power supply pins (v dd , v ss ) . . . . . . . . . . . . . . . . . . . . . . . 33 1.6.2 voltage regulat or output pin (v reg ). . . . . . . . . . . . . . . . . . 34 1.6.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.6.4 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 external interrupt pins (irq , pte4/d?) . . . . . . . . . . . . . . . . 35 1.6.6 analog power supply pins (v dda , v ssa ) . . . . . . . . . . . . . . . 35 1.6.7 analog voltage regulator out (v rega ) . . . . . . . . . . . . . . . . 35 1.6.8 port a input/output (i/o) pins (pta7/kba7/ad7?pta0/kba0/ad0) . . . . . . . . . . . . . . . 36 1.6.9 port b i/o pins (ptb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.10 port c i/o pins (ptc1/rxd, ptc0 /txd) . . . . . . . . . . . . . . . 36 1.6.11 port d i/o pins (ptd3?p td0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.12 port e i/o pins (pte4/ d?, pte3/d+, pte2/t2ch01, pte1/t1ch01, pte0/tclk). . . . . . . . . . . . . . . . . . . . . . 36 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 39 table of contents technical data MC68HC908JG16 ? rev. 1.1 8 table of contents freescale semiconductor 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.8.1 flash block protect regi ster . . . . . . . . . . . . . . . . . . . . . . . 64 4.9 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.9.1 variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.9.2 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.9.3 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.9.4 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table of contents MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor table of contents 9 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 section 7. oscillator (osc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.3 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .92 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 93 7.4.2 crystal amplifier out put pin (osc1) . . . . . . . . . . . . . . . . . . 93 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 93 7.4.4 crystal output frequency signal (oscxclk). . . . . . . . . . . 93 7.4.5 clock doubler out (oscdclk) . . . . . . . . . . . . . . . . . . . . . . 93 7.4.6 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table of contents technical data MC68HC908JG16 ? rev. 1.1 10 table of contents freescale semiconductor 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . 94 section 8. system integration module (sim) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 98 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.2 clock startup from po r or lvi reset . . . . . . . . . . . . . . . . . 99 8.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 99 8.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 99 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 101 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 8.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 103 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 104 8.4.2.6 universal serial bus (usb) rese t . . . . . . . . . . . . . . . . . 104 8.4.2.7 registers values after different resets. . . . . . . . . . . . . 104 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 105 8.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 106 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 106 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2.3 interrupt stat us register 3 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 113 table of contents MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor table of contents 11 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 117 8.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 118 8.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . . 119 section 9. monitor rom (mon) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 9.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.5.1 extended security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 section 10. timer interface module (tim) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 142 10.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .143 table of contents technical data MC68HC908JG16 ? rev. 1.1 12 table of contents freescale semiconductor 10.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 143 10.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 144 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 145 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.9.1 tim clock pin (pte0/tc lk) . . . . . . . . . . . . . . . . . . . . . . .149 10.9.2 tim channel i/o pins (pte 1/t1ch01:pte2/t2ch01) . . . 149 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 150 10.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.10.3 tim counter modulo r egisters . . . . . . . . . . . . . . . . . . . . . 153 10.10.4 tim channel status and control registers . . . . . . . . . . . . 154 10.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 section 11. universal se rial bus module (usb) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.5.1 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.5.1.1 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.5.1.2 packet identifier fiel d . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.5.1.3 address field (addr) . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.1.4 endpoint field (endp) . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.1.5 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . 170 11.5.1.6 end-of-packet (eop) . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.5.2 reset signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table of contents MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor table of contents 13 11.5.3 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.5.4 resume after suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.4.1 host initiated resume . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.4.2 usb reset signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.5.4.3 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.5.5 low-speed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.6 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.7 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.2 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.2.1 output driver charac teristics . . . . . . . . . . . . . . . . . . . . . 176 11.7.2.2 low speed (1.5 m bps) driver characterist ics . . . . . . . . 176 11.7.2.3 receiver data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.4 data source jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.5 data signal rise and fall time . . . . . . . . . . . . . . . . . . . 178 11.7.3 usb control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.8.1 usb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.8.2 usb interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.8.3 usb interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.8.4 usb interrupt register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.8.5 usb control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.8.6 usb control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.8.7 usb control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.8.8 usb control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.8.9 usb control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.8.10 usb status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.8.11 usb status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.8.12 usb endpoint 0 data r egisters . . . . . . . . . . . . . . . . . . . . . 196 11.8.13 usb endpoint 1 data r egisters . . . . . . . . . . . . . . . . . . . . . 197 11.8.14 usb endpoint 2 data r egisters . . . . . . . . . . . . . . . . . . . . . 198 11.9 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.9.1 usb end-of-transaction interrupt . . . . . . . . . . . . . . . . . . . 199 11.9.1.1 receive control endpoint 0 . . . . . . . . . . . . . . . . . . . . . . 200 11.9.1.2 transmit control endpoint 0 . . . . . . . . . . . . . . . . . . . . . 202 11.9.1.3 transmit endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table of contents technical data MC68HC908JG16 ? rev. 1.1 14 table of contents freescale semiconductor 11.9.1.4 transmit endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.1.5 receive endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.2 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.3 end-of-packet interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 section 12. serial communic ations interface module (sci) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.5.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 215 12.5.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .220 12.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .226 12.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table of contents MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor table of contents 15 12.8.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.8.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.9.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.9.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.9.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 12.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . .242 section 13. analog-to-dig ital converter (adc) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 13.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 13.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 13.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.7.1 adc analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 250 13.7.2 adc analog ground pin (v ssa ). . . . . . . . . . . . . . . . . . . . . 250 13.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 250 13.7.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 250 13.7.5 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .251 table of contents technical data MC68HC908JG16 ? rev. 1.1 16 table of contents freescale semiconductor 13.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 253 section 14. input/output (i/o) ports 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 14.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.5.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . 264 14.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 267 14.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 271 14.8 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 14.8.1 port option control register . . . . . . . . . . . . . . . . . . . . . . .273 section 15. external interrupt (irq) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 15.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 15.6 pte4/d? pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table of contents MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor table of contents 17 15.7 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 279 15.8 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 280 15.9 irq option control regist er. . . . . . . . . . . . . . . . . . . . . . . . . . 281 section 16. keyboard in terrupt module (kbi) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 16.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.7.1 keyboard status and control register. . . . . . . . . . . . . . . . 288 16.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 289 16.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 16.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 16.9 keyboard module during break interrupts . . . . . . . . . . . . . . . 290 section 17. computer op erating properly (cop) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 17.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.1 oscdclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 17.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 17.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 table of contents technical data MC68HC908JG16 ? rev. 1.1 18 table of contents freescale semiconductor 17.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 294 17.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 17.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 17.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 17.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 17.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 17.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 17.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 296 section 18. low-volt age inhibit (lvi) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 18.4.1 low v dd detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 18.4.2 low v reg detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 18.5 lvi control and configur ation . . . . . . . . . . . . . . . . . . . . . . . . 299 18.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 18.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 section 19. break module (brk) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 19.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 304 19.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .304 19.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 304 19.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 304 table of contents MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor table of contents 19 19.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 19.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 19.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 305 19.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 308 section 20. electrical specifications 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 20.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 310 20.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 311 20.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 20.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 312 20.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 20.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 20.9 timer interface module characterist ics . . . . . . . . . . . . . . . . . 314 20.10 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 314 20.11 usb low-speed source electrical characteri stics . . . . . . . . 315 20.12 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.13 adc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . 317 20.14 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 318 section 21. mechanic al specifications 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 21.3 32-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 320 table of contents technical data MC68HC908JG16 ? rev. 1.1 20 table of contents freescale semiconductor section 22. ordering information 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 22.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor list of figures 21 technical data ? MC68HC908JG16 list of figures figure title page 1-1 MC68HC908JG16 mcu block diagram. . . . . . . . . . . . . . . . . . 32 1-2 32-pin lqfp pin a ssignment . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1-3 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1-4 regulator supply capacit or configuration . . . . . . . . . . . . . . . . 34 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .42 4-1 flash i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 58 4-2 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 59 4-3 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 63 4-4 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 64 4-5 flash block protec t start address . . . . . . . . . . . . . . . . . . . . .64 5-1 configuration register (config). . . . . . . . . . . . . . . . . . . . . . . 70 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 78 7-1 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .92 8-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .98 8-3 sim clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 8-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 8-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 list of figures technical data MC68HC908JG16 ? rev. 1.1 22 list of figures freescale semiconductor figure title page 8-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8-8 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8-9 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8-10 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 109 8-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . 110 8-13 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . . 112 8-14 interrupt status register 3 (int3). . . . . . . . . . . . . . . . . . . . . . 112 8-15 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8-16 wait recovery from interrupt or br eak . . . . . . . . . . . . . . . . . . 115 8-17 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 115 8-18 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8-19 stop mode recovery fr om interrupt or break . . . . . . . . . . . . . 116 8-20 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 117 8-21 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 118 8-22 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 119 9-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9-2 low-voltage monitor m ode entry flowchart. . . . . . . . . . . . . . 125 9-3 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9-4 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 9-5 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 9-6 write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9-7 stack pointer at monitor mode entry . . . . . . . . . . . . . . . . . . . 132 9-8 monitor mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . .133 10-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .139 10-3 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 144 10-4 tim status and control register (tsc ) . . . . . . . . . . . . . . . . . 150 10-5 tim counter registers high (tcnth) . . . . . . . . . . . . . . . . . . 152 10-6 tim counter registers low (tcntl) . . . . . . . . . . . . . . . . . . . 153 10-7 tim counter modulo r egister high (tmodh) . . . . . . . . . . . . 153 10-8 tim counter modulo r egister low (tmodl) . . . . . . . . . . . . . 153 10-9 tim channel 0 status and control register (tsc0) . . . . . . . 154 list of figures MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor list of figures 23 figure title page 10-10 tim channel 1 status and control register (t sc1) . . . . . . . 154 10-11 chxmax latenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 10-12 tim channel 0 register high (tch0h) . . . . . . . . . . . . . . . . . 158 10-13 tim channel 0 register low (tch0l) . . . . . . . . . . . . . . . . . . 158 10-14 tim channel 1 register high (tch1h) . . . . . . . . . . . . . . . . . 158 10-15 tim channel 1 register low (tch1l) . . . . . . . . . . . . . . . . . . 158 11-1 usb i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11-2 usb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11-3 supported transaction types per en dpoint. . . . . . . . . . . . . . 167 11-4 supported usb packet types . . . . . . . . . . . . . . . . . . . . . . . . 168 11-5 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11-6 sop, sync signaling, and voltage lev els . . . . . . . . . . . . . . . 169 11-7 eop transaction voltage levels . . . . . . . . . . . . . . . . . . . . . . 171 11-8 eop width timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11-9 external low-speed device configurat ion . . . . . . . . . . . . . . . 174 11-10 regulator electrical connections . . . . . . . . . . . . . . . . . . . . . . 175 11-11 receiver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11-12 differential input sensitivity range. . . . . . . . . . . . . . . . . . . . . 177 11-13 data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11-14 data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . .178 11-15 usb address register ( uaddr) . . . . . . . . . . . . . . . . . . . . . . 180 11-16 usb interrupt register 0 (uir0) . . . . . . . . . . . . . . . . . . . . . . . 181 11-17 usb interrupt register 1 (uir1) . . . . . . . . . . . . . . . . . . . . . . . 183 11-18 usb interrupt register 2 (uir2) . . . . . . . . . . . . . . . . . . . . . . . 186 11-19 usb control register 0 (ucr0) . . . . . . . . . . . . . . . . . . . . . . . 187 11-20 usb control register 1 (ucr1) . . . . . . . . . . . . . . . . . . . . . . . 188 11-21 usb control register 2 (ucr2) . . . . . . . . . . . . . . . . . . . . . . . 189 11-22 usb control register 3 (ucr3) . . . . . . . . . . . . . . . . . . . . . . . 191 11-23 usb control register 4 (ucr4) . . . . . . . . . . . . . . . . . . . . . . . 193 11-24 usb status register 0 (usr0). . . . . . . . . . . . . . . . . . . . . . . . 194 11-25 usb status register 2 (usr1). . . . . . . . . . . . . . . . . . . . . . . . 195 11-26 usb endpoint 0 data registers (ue0d0?ue0d7 ). . . . . . . . . 196 11-27 usb endpoint 1 data registers (ue1d0?ue1d7 ). . . . . . . . . 197 11-28 usb endpoint 2 data registers (ue2d0?ue2d7 ). . . . . . . . . 198 11-29 out token data flow for receive endpoint 0. . . . . . . . . . . . 200 list of figures technical data MC68HC908JG16 ? rev. 1.1 24 list of figures freescale semiconductor figure title page 11-30 setup token data flow for receiv e endpoint 0 . . . . . . . . . 201 11-31 in token data flow for transmit endpoint 0 . . . . . . . . . . . . . 202 11-32 in token data flow for transmit endpoint 1 . . . . . . . . . . . . . 203 12-1 sci module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .209 12-2 sci i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .210 12-3 sci data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 12-4 sci transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12-5 sci receiver block diagr am . . . . . . . . . . . . . . . . . . . . . . . . . 217 12-6 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12-7 slow data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 12-8 fast data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 12-9 sci control regist er 1 (scc1). . . . . . . . . . . . . . . . . . . . . . . . 228 12-10 sci control regist er 2 (scc2). . . . . . . . . . . . . . . . . . . . . . . . 231 12-11 sci control regist er 3 (scc3). . . . . . . . . . . . . . . . . . . . . . . . 233 12-12 sci status register 1 (s cs1) . . . . . . . . . . . . . . . . . . . . . . . . 236 12-13 flag clearing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 12-14 sci status register 2 (s cs2) . . . . . . . . . . . . . . . . . . . . . . . . 240 12-15 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . .241 12-16 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . . . 242 13-1 adc i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 13-3 adc status and control register (adscr) . . . . . . . . . . . . . . 251 13-4 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13-5 adc input clock register (adiclk) . . . . . . . . . . . . . . . . . . . 253 14-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .256 14-2 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 259 14-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 14-5 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 261 14-7 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 14-8 port c data register (ptc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14-9 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . 264 list of figures MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor list of figures 25 figure title page 14-10 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 14-11 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14-12 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 267 14-13 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 14-14 port e data register (pte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14-15 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 271 14-16 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 14-17 port option control regi ster (pocr). . . . . . . . . . . . . . . . . . . 273 15-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 277 15-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .277 15-3 irq status and control register (iscr) . . . . . . . . . . . . . . . . 280 15-4 irq option control regist er (iocr) . . . . . . . . . . . . . . . . . . . 281 16-1 i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 16-2 keyboard module block di agram . . . . . . . . . . . . . . . . . . . . . . 285 16-3 keyboard status and control register (kbscr) . . . . . . . . . . 288 16-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 289 17-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 17-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . . 294 17-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 295 18-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .298 18-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . . 299 19-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 303 19-2 break module i/o register summary . . . . . . . . . . . . . . . . . . . 303 19-3 break status and control register (brkscr). . . . . . . . . . . . 305 19-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 306 19-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 306 19-6 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 307 19-7 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 308 21-1 32-pin lqfp (cas e #873a) . . . . . . . . . . . . . . . . . . . . . . . . . . 320 list of figures technical data MC68HC908JG16 ? rev. 1.1 26 list of figures freescale semiconductor MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor list of tables 27 technical data ? MC68HC908JG16 list of tables table title page 1-1 summary of pin fu nctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4-1 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4-2 summary of flash routin e variables . . . . . . . . . . . . . . . . . . 66 4-3 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4-4 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4-5 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8-1 sim module signal name conventions . . . . . . . . . . . . . . . . . . 97 8-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8-3 registers not affected by normal re set. . . . . . . . . . . . . . . . . 105 8-4 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9-1 mode entry requirements and options . . . . . . . . . . . . . . . . . 124 9-2 monitor mode vector diffe rences . . . . . . . . . . . . . . . . . . . . . . 126 9-3 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 127 9-4 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 129 9-5 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 130 9-6 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 130 9-7 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 131 9-8 readsp (read stack po inter) command . . . . . . . . . . . . . . . 131 9-9 run (run user program) command . . . . . . . . . . . . . . . . . . . 132 9-10 monitor mode security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 list of tables technical data MC68HC908JG16 ? rev. 1.1 28 list of tables freescale semiconductor table title page 10-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 156 11-1 usb module pin name c onventions . . . . . . . . . . . . . . . . . . . 162 11-2 supported packet ident ifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 169 12-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12-2 start bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 12-3 data bit recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 12-4 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 12-5 character format selection . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12-6 sci baud rate prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 12-7 sci baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12-8 sci baud rate selection examples . . . . . . . . . . . . . . . . . . . .244 13-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 14-1 port control register bits summary. . . . . . . . . . . . . . . . . . . .257 14-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 14-3 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 14-4 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 14-5 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 14-6 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 22-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor general description 29 technical data ? MC68HC908JG16 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 1.6.1 power supply pins (v dd , v ss ) . . . . . . . . . . . . . . . . . . . . . . . 33 1.6.2 voltage regulat or output pin (v reg ). . . . . . . . . . . . . . . . . . 34 1.6.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.6.4 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 external interrupt pins (irq , pte4/d?) . . . . . . . . . . . . . . . . 35 1.6.6 analog power supply pins (v dda , v ssa ) . . . . . . . . . . . . . . . 35 1.6.7 analog voltage regulator out (v rega ) . . . . . . . . . . . . . . . . 35 1.6.8 port a input/output (i/o) pins (pta7/kba7/ad7?pta0/kba0/ad0) . . . . . . . . . . . . . . . 36 1.6.9 port b i/o pins (ptb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.10 port c i/o pins (ptc1/rxd, ptc0 /txd) . . . . . . . . . . . . . . . 36 1.6.11 port d i/o pins (ptd3?p td0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.12 port e i/o pins (pte4/ d?, pte3/d+, pte2/t2ch01, pte1/t1ch01, pte0/tclk). . . . . . . . . . . . . . . . . . . . . . 36 1.2 introduction the MC68HC908JG16 is a member of the low-cost, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. general description technical data MC68HC908JG16 ? rev. 1.1 30 general description freescale semiconductor 1.3 features features of the mc 68hc908jg16 mcu incl ude the following: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families low-power design; fully st atic with stop and wait modes 6-mhz internal bus frequency 16,384 bytes of on-chip fl ash memory with security 1 feature 384 bytes of on-chip rand om access memory (ram) up to 20 general-purpose input /output (i/o) pins, including: ? 15 shared-function i/o pins ? 8-bit keyboard interrupt port ? 10ma high current drive fo r ps/2 connection on 2 pins (with usb module disabled) ? 5 dedicated i/o pins, with 25ma direct drive for infrared led on 2 pins and 10ma direct dr ive for normal led on 2 pins two 16-bit, 2-channel timer inte rface modules (tim1 and tim2) with selectable input capture, output compar e, pwm capability on each channel, and external clock input option (tclk) universal serial bus specific ation 2.0 low-speed functions: ? 1.5mbps data rate ? on-chip 3.3v regulator ? endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer ? endpoint 1 with 8-byte transmit buffer ? endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer serial communications interface module (sci) 8-channel, 8-bit analog-to-d igital converter (adc) 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. general description mcu block diagram MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor general description 31 in-circuit programming capabilit y using usb communication or standard serial li nk on pta0 pin system protection features: ? optional computer operati ng properly (cop) reset ? optional low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset master reset pin with intern al pull-up and power-on reset irq interrupt pin with internal pull-up and schmi tt-trigger input 32-pin low-profile quad flat pack (lqfp) features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support 1.4 mcu block diagram figure 1-1 shows the structure of the MC68HC908JG16. general description technical data MC68HC908JG16 ? rev. 1.1 32 general description freescale semiconductor figure 1-1. mc68hc908j g16 mcu block diagram system integration module 2-channel timer interface module 1 low voltage inhibit module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash memory ? 16,384 bytes user ram ? 384 bytes monitor rom ? 1,472 bytes user flash vectors ? 48 bytes power and internal pta ddra ddre pte usb module usb endpoint 0, 1, 2 ls usb transceiver break module oscillator ptc ddrc keyboard interrupt module power-on reset module (1) osc1 (1) osc2 (2) rst (3) irq v dd v ss v reg (3.3v) 2-channel timer interface module 2 serial communications interface module irq module voltage regulators pte0/tclk (3) pte1/t1ch01 (3) pte2/t2ch01 (3) pte3/d+ (3), (4) pte4/d? (3), (4) ptc1/rxd (3) ptc0/txd (3) pta7/kba7 /ad7 pta0/kba0 /ad0 (1) pins have 3v logic. (2) pins have integrated pullup device. (3) pins have software co nfigurable pul l-up device. (4) pins are open-drain when configured as output. : (3) v dda v ssa v rega (3.3v) 8-bit analog-to-digital converter module v refh v refl ptb ddrb ptb0 (3) ptd ddrd ptd3?ptd0 (4) general description pin assignments MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor general description 33 1.5 pin assignments figure 1-2. 32-pin lqfp pin assignment 1.6 pin functions description of pin func tions are provided here. 1.6.1 power supply pins (v dd , v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take care to provide power supply bypassing at the mcu as shown in figure 1-3 . pta0/kba0/ad0 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 24 20 19 18 17 9 osc2 vreg vdd ptd0 ptd1 ptd2 ptd3 pte1/t1ch01 ptc1/rxd ptc0/txd pte4/d? pte3/d+ irq pta7/kba7/ad7 pta5/kba5/ad5 pta6/kba6/ad6 vrefh pta3/kba3/ad3 pta2/kba2/ad2 pte2/t2ch01 pte0/tclk pta4/kba4/ad4 ptb0 vrefl osc1 23 22 21 rst vssa vrega vdda pta1/kba1/ad1 vss general description technical data MC68HC908JG16 ? rev. 1.1 34 general description freescale semiconductor place the bypass capacitors as cl ose to the mcu power pins as possible. use high-frequency-res ponse ceramic capacitors for c bypass . c bulk are optional bulk current bypass ca pacitors for use in applications that require the port pins to source high current levels. figure 1-3. power supply bypassing 1.6.2 voltage regulator output pin (v reg ) v reg is the 3.3v output of the on-chip voltage regulator. v reg is used internally for the mcu oper ation and the usb data driv er. it is also used to supply the volt age for the external pullup re sistor required on the usb?s d? line. the v reg pin requires an exte rnal bulk capacitor 4.7 f or larger and a 0.1 f ceramic bypass capacitor as figure 1-4 shows. place the bypass capacitor s as close to the v reg pin as possible. figure 1-4. regulator s upply capacitor configuration mcu c bulk c bypass 0.1 f + note: values shown are typical values. v dd v dd v ss mcu c regbulk c regbypass 0.1 f v ss + v reg > 4.7 f general description pin functions MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor general description 35 1.6.3 oscillator pins (osc1 and osc2) the osc1 and osc2 pins ar e the connections for the on-chip oscillator circuit. 1.6.4 external reset pin (rst ) a logic zero on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowin g a reset of the entire system. it is driven low when any internal reset s ource is asserted. the rst pin contains an internal pullup device to v dd . (see section 8. system integration module (sim) .) 1.6.5 external interrupt pins (irq , pte4/d?) irq is an asynchronous exter nal interrupt pin. irq is also the pin to enter monitor mode. the irq pin contains a softwa re configurable pullup device to v dd . pte4/d? can be programmed to trigger the irq interrupt. (see section 15. exter nal interrupt (irq) .) 1.6.6 analog power supply pins (v dda , v ssa ) v dda and v ssa are the power supply and ground pins for the analog portion of the mcu. connect v dda to the same voltage potential as v dd . connect v ssa to the same voltage potential as v ss . decoupling of these pins should be as per the digital supply. 1.6.7 analog voltage regulator out (v rega ) v rega is the 3.3v output of the seco nd on-chip voltage regulator. v rega is used for adc operation . decoupling of this pi n should be as per the digital v reg . general description technical data MC68HC908JG16 ? rev. 1.1 36 general description freescale semiconductor 1.6.8 port a input/output (i/o) pins (pta7/kba7 /ad7?pta0/kba0 /ad0) port a is a 8-bit special function port that shares its pins with the analog- to-digital converter and key board interrupt module. (see section 14. input/output (i/o) ports , section 13. an alog-to-digital converter (adc) , and section 16. keyboard in terrupt module (kbi) .) each pin contains a software conf igurable pullup device to v dd when the pin is configured as an input. (see 14.8 port options .) 1.6.9 port b i/o pins (ptb0) port b is an 1-bit general -purpose bidirectional i/ o port pin and contains a software configurable pullup device to v dd when the pin is configured as an input. (see section 14. input/output (i/o) ports and 14.8 port options .) 1.6.10 port c i/o pins (ptc1/rxd, ptc0/txd) port c is a 2-bit special function port that shares its pins with the sci module. (see section 14. input/o utput (i/o) ports .) each pin contains a software configurable pullup device to v dd when the pin is configured as an input. (see 14.8 port options .) 1.6.11 port d i/o pins (ptd3?ptd0) ptd3?ptd0 are general-purpose bidire ctional i/o port pins; open-drain when configured as output. (see section 14. input/o utput (i/o) ports .) ptd3?ptc2 are software configurable to be 10ma sink pins for direct led connections. ptd1?ptd0 are so ftware configurable to be 25ma sink pins for direct in frared led connec tions. (see 14.8 port options .) 1.6.12 port e i/o pins (pte4/d?, pte3/d+, pte2/t2ch01, pte1/t1ch01, pte0/tclk) port e is a 5-bit special function port that shares two of its pins with the usb module and three of its pins with the two ti mer interface modules. each pte2?pte0 pin contains a so ftware configurable pullup device to v dd when the pin is configur ed as an input or output. general description pin functions MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor general description 37 when the usb module is disabled, the pte4 and pte3 pins are general-purpose bidirectional i/o port pins with 10ma sink capability. each pin is open-dr ain when configured as an output; and each pin contains a softwa re configurable 5k ? pullup to v dd when configured as an input . the pte4 pin can also be enabled to trigger the irq interrupt. when the usb module is enabled, the pte4/d? and pte3/d+ pins become the usb module d? and d+ pins. the usb d? pin contains a 1.5k ? software configurable pullup device to v reg . (see section 10. timer interface module (tim) , section 11. universal serial bus module (usb) and section 14. input/o utput (i/o) ports .) note: any unused inputs and i/o po rts should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the MC68HC908JG16 do not require te rmination, termination is recommended to reduce the possi bility of static damage. summary of the pin func tions are provided in table 1-1 . table 1-1. summary of pin functions pin name pin description in/out voltage level v dd power supply. in 4.0 to 5.5v v ss power supply ground. out 0v v reg 3.3v regulated output from mcu. out v reg (3.3v) rst reset input, active low. with internal pull-up and schmitt trigger input. in/out v dd irq external irq pin; with programmable internal pull-up and schmitt trigger input. in v dd used for mode entry selection. in v reg to v tst osc1 crystal oscillator input. in v reg osc2 crystal oscillator output; inverting of osc1 signal. out v reg v dda analog power supply. in 4.0 to 5.5v v ssa analog power supply ground. out 0v v rega 3.3v regulated output from mcu. out v rega (3.3v) general description technical data MC68HC908JG16 ? rev. 1.1 38 general description freescale semiconductor pta0/kba0 /ad0 : pta7/kba7 /ad7 8-bit general purpose i/o port. in/out v dd pins as keyboard interrupts, kba0 ?kba7 .in v dd each pin has programmable internal pullup when configured as input. in v dd each pin can be configured as adc input channel. in v ssa to v rega ptc0/txd ptc1/rxd 2-bit general purpose i/o port. in/out v dd each pin has programmable internal pull-up device. in v dd ptc0 as txd of sci module. out v dd ptc1 as rxd of sci module. in v dd ptd0?ptd3 4-bit general purpose i/o port; open-drain when configured as output. in out v dd v reg or v dd ptd0?ptd1 have configurable 25ma sink for infrared led. out v reg or v dd ptd2?ptd3 have configurable 10ma sink for led. out v reg or v dd pte0/tclk pte1/t1ch01 pte2/t2ch01 pte0?pte2 are general purpose i/o lines. in/out v dd pte0?pte2 have programmable internal pullup when configured as input or output. in/out v dd pte0 as tclk of tim1 and tim2. in v dd pte1 as t1ch01 of tim1. in/out v dd pte2 as t2ch01 of tim2. in/out v dd pte3/d+ pte4/d? pte3?pte4 general purpose i/o lines; open-drain when configured as output. in out v dd v reg or v dd pte3?pte4 have programmable internal pullup when configured as input. in v dd pte3 as d+ of usb module. in/out v reg pte4 as d? of usb module. in/out v reg pte4 as additional irq interrupt. in v dd table 1-1. summary of pin functions pin name pin description in/out voltage level MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor memory map 39 technical data ? MC68HC908JG16 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 39 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2 introduction the cpu08 can address 64k-bytes of memory space. the memory map, shown in figure 2-1 , includes: 16,384 bytes of flash memory 384 bytes of random-access memory (ram) 48 bytes of user-defined vectors 1,024 + 448 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented locati on can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. memory map technical data MC68HC908JG16 ? rev. 1.1 40 memory map freescale semiconductor 2.4 reserved me mory locations accessing a reserved location can hav e unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserv ed or with the letter r. 2.5 input/output (i/o) section most of the control, st atus, and data registers ar e in the zero page area of $0000?$007f. additional i/o registers have these addresses: $fe00; sim break st atus register, sbsr $fe01; sim reset st atus register, srsr $fe02; reserved $fe03; sim break flag control register, sbfcr $fe04; interrupt stat us register 1, int1 $fe05; interrupt stat us register 2, int2 $fe06; interrupt stat us register 3, int3 $fe07; reserved $fe08; flash contro l register, flcr $fe09; flash block protect register, flbpr $fe0a; reserved $fe0b; reserved $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; reserved $ffff; cop control register, copctl data registers are shown in figure 2-2 . table 2-1 is a list of vector locations. memory map input/output (i/o) section MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor memory map 41 $0000 $007f i/o registers 128 bytes $0080 $01ff ram 384 bytes $0200 $b9ff unimplemented 47,104 bytes $ba00 $f9ff flash memory 16,384 bytes $fa00 $fdff monitor rom 1 1,024 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 flash control register (flcr) $fe09 flash block protect register (flbpr) $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and co ntrol register (brkscr) $fe0f reserved $fe10 $ffcf monitor rom 2 448 bytes $ffd0 $ffff flash vectors 48 bytes figure 2-1. memory map memory map technical data MC68HC908JG16 ? rev. 1.1 42 memory map freescale semiconductor addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: 0000000 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 000000 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 0 0 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:0*0000000 * ddra7 bit is reset by por or lvi reset only. $0005 data direction register b (ddrb) read: 0000000 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: 000000 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: 0 0 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 12) memory map input/output (i/o) section MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor memory map 43 $000a timer 1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000b reserved read: rrrrrrrr write: reset: $000c timer 1 counter register high (t1cnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d timer 1 counter register low (t1cntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e timer 1 counter modulo register high (t1modh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f timer 1 counter modulo register low (t1modl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 timer 1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 timer 1 channel 0 register high (t1ch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 timer 1 channel 0 register low (t1ch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 timer 1 channel 1 status and control register (t1sc1) read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 12) memory map technical data MC68HC908JG16 ? rev. 1.1 44 memory map freescale semiconductor $0014 timer 1 channel 1 register high (t1ch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 timer 1 channel 1 register low (t1ch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0016 keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $0017 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $0018 usb interrupt register 2 (uir2) read: 00000000 write: eopfr rstfr txd2fr rxd2fr tdx1fr resumfr txd0fr rxd0fr reset:00000000 $0019 usb control register 2 (ucr2) read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 $001a usb control register 3 (ucr3) read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 * pullen bit is reset by por or lvi reset only. $001b usb control register 4 (ucr4) read: 00000 fusbo fdp fdm write: reset:00000000 $001c irq option control register (iocr) read: 00000pte4if pte4ie irqpd write: reset:00000000 $001d port option control register (pocr) read: pte20p ptdldd ptdildd pte4p pte3p pcp pbp pap write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 12) memory map input/output (i/o) section MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor memory map 45 $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 $001f configuration register (config) ? read: lvidr lvi5or3 urstd lvid ssrec coprs stop copd write: reset:0*0*0*0*0000 ? one-time writable register after each reset. * lvidr, lvi5or3, urstd, and lvid, are reset by por or lvi reset only. $0020 usb endpoint 0 data register 0 (ue0d0) read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t 04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset $0021 usb endpoint 0 data register 1 (ue0d1) read: ue0r17 ue0r16 ue0r15 ue0r14 ue0r13 ue0r12 ue0r11 ue0r10 write: ue0t17 ue0t16 ue0t15 ue0t 14 ue0t13 ue0t12 ue0t11 ue0t10 reset: unaffected by reset $0022 usb endpoint 0 data register 2 (ue0d2) read: ue0r27 ue0r26 ue0r25 ue0r24 ue0r23 ue0r22 ue0r21 ue0r20 write: ue0t27 ue0t26 ue0t25 ue0t 24 ue0t23 ue0t22 ue0t21 ue0t20 reset: unaffected by reset $0023 usb endpoint 0 data register 3 (ue0d3) read: ue0r37 ue0r36 ue0r35 ue0r34 ue0r33 ue0r32 ue0r31 ue0r30 write: ue0t37 ue0t36 ue0t35 ue0t 34 ue0t33 ue0t32 ue0t31 ue0t30 reset: unaffected by reset $0024 usb endpoint 0 data register 4 (ue0d4) read: ue0r47 ue0r46 ue0r45 ue0r44 ue0r43 ue0r42 ue0r41 ue0r40 write: ue0t47 ue0t46 ue0t45 ue0t 44 ue0t43 ue0t42 ue0t41 ue0t40 reset: unaffected by reset $0025 usb endpoint 0 data register 5 (ue0d5) read: ue0r57 ue0r56 ue0r55 ue0r54 ue0r53 ue0r52 ue0r51 ue0r50 write: ue0t57 ue0t56 ue0t55 ue0t 54 ue0t53 ue0t52 ue0t51 ue0t50 reset: unaffected by reset $0026 usb endpoint 0 data register 6 (ue0d6) read: ue0r67 ue0r66 ue0r65 ue0r64 ue0r63 ue0r62 ue0r61 ue0r60 write: ue0t67 ue0t66 ue0t65 ue0t 64 ue0t63 ue0t62 ue0t61 ue0t60 reset: unaffected by reset $0027 usb endpoint 0 data register 7 (ue0d7) read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t 74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 12) memory map technical data MC68HC908JG16 ? rev. 1.1 46 memory map freescale semiconductor $0028 usb endpoint 1 data register 0 (ue1d0) read: write: ue1t07 ue1t06 ue1t05 ue1t 04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset $0029 usb endpoint 1 data register 1 (ue1d1) read: write: ue1t17 ue1t16 ue1t15 ue1t 14 ue1t13 ue1t12 ue1t11 ue1t10 reset: unaffected by reset $002a usb endpoint 1 data register 2 (ue1d2) read: write: ue1t27 ue1t26 ue1t25 ue1t 24 ue1t23 ue1t22 ue1t21 ue1t20 reset: unaffected by reset $002b usb endpoint 1 data register 3 (ue1d3) read: write: ue1t37 ue1t36 ue1t35 ue1t 34 ue1t33 ue1t32 ue1t31 ue1t30 reset: unaffected by reset $002c usb endpoint 1 data register 4 (ue1d4) read: write: ue1t47 ue1t46 ue1t45 ue1t 44 ue1t43 ue1t42 ue1t41 ue1t40 reset: unaffected by reset $002d usb endpoint 1 data register 5 (ue1d5) read: write: ue1t57 ue1t56 ue1t55 ue1t 54 ue1t53 ue1t52 ue1t51 ue1t50 reset: unaffected by reset $002e usb endpoint 1 data register 6 (ue1d6) read: write: ue1t67 ue1t66 ue1t65 ue1t 64 ue1t63 ue1t62 ue1t61 ue1t60 reset: unaffected by reset $002f usb endpoint 1 data register 7 (ue1d7) read: write: ue1t77 ue1t76 ue1t75 ue1t 74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset $0030 usb endpoint 2 data register 0 (ue2d0) read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t 04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset $0031 usb endpoint 2 data register 1 (ue2d1) read: ue2r17 ue2r16 ue2r15 ue2r14 ue2r13 ue2r12 ue2r11 ue2r10 write: ue2t17 ue2t16 ue2t15 ue2t 14 ue2t13 ue2t12 ue2t11 ue2t10 reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 12) memory map input/output (i/o) section MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor memory map 47 $0032 usb endpoint 2 data register 2 (ue2d2) read: ue2r27 ue2r26 ue2r25 ue2r24 ue2r23 ue2r22 ue2r21 ue2r20 write: ue2t27 ue2t26 ue2t25 ue2t 24 ue2t23 ue2t22 ue2t21 ue2t20 reset: unaffected by reset $0033 usb endpoint 2 data register 3 (ue2d3) read: ue2r37 ue2r36 ue2r35 ue2r34 ue2r33 ue2r32 ue2r31 ue2r30 write: ue2t37 ue2t36 ue2t35 ue2t 34 ue2t33 ue2t32 ue2t31 ue2t30 reset: unaffected by reset $0034 usb endpoint 2 data register 4 (ue2d4) read: ue2r47 ue2r46 ue2r45 ue2r44 ue2r43 ue2r42 ue2r41 ue2r40 write: ue2t47 ue2t46 ue2t45 ue2t 44 ue2t43 ue2t42 ue2t41 ue2t40 reset: unaffected by reset $0035 usb endpoint 2 data register 5 (ue2d5) read: ue2r57 ue2r56 ue2r55 ue2r54 ue2r53 ue2r52 ue2r51 ue2r50 write: ue2t57 ue2t56 ue2t55 ue2t 54 ue2t53 ue2t52 ue2t51 ue2t50 reset: unaffected by reset $0036 usb endpoint 2 data register 6 (ue2d6) read: ue2r67 ue2r66 ue2r65 ue2r64 ue2r63 ue2r62 ue2r61 ue2r60 write: ue2t67 ue2t66 ue2t65 ue2t 64 ue2t63 ue2t62 ue2t61 ue2t60 reset: unaffected by reset $0037 usb endpoint 2 data register 7 (ue2d7) read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t 74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset $0038 usb address register (uaddr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:0*0000000 * usben bit is reset by por or lvi reset only. $0039 usb interrupt register 0 (uir0) read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 $003a usb interrupt register 1 (uir1) read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 $003b usb control register 0 (ucr0) read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 6 of 12) memory map technical data MC68HC908JG16 ? rev. 1.1 48 memory map freescale semiconductor $003c usb control register 1 (ucr1) read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $003d usb status register 0 (usr0) read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset $003e usb status register 1 (usr1) read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u000uuuu $003f unimplemented read: write: $0040 timer 2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0041 reserved read: rrrrrrrr write: reset: $0042 timer 2 counter register high (t2cnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $0043 timer 2 counter register low (t2cntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $0044 timer 2 counter modulo register high (t2modh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $0045 timer 2 counter modulo register low (t2modl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 7 of 12) memory map input/output (i/o) section MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor memory map 49 $0046 timer 2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0047 timer 2 channel 0 register high (t2ch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0048 timer 2 channel 0 register low (t2ch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0049 timer 2 channel 1 status and control register (t2sc1) read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $004a timer 2 channel 1 register high (t2ch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $004b timer 2 channel 1 register low (t2ch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $004c reserved read: rrrrrrrr write: reset: $004d reserved read: rrrrrrrr write: reset: $004e reserved read: rrrrrrrr write: reset: $004f reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 8 of 12) memory map technical data MC68HC908JG16 ? rev. 1.1 50 memory map freescale semiconductor $0050 reserved read: rrrrrrrr write: reset: $0051 reserved read: rrrrrrrr write: reset: $0052 reserved read: rrrrrrrr write: reset: $0053 reserved read: rrrrrrrr write: reset: $0054 reserved read: rrrrrrrr write: reset: $0055 reserved read: rrrrrrrr write: reset: $0056 reserved read: rrrrrrrr write: reset: $0057 reserved read: rrrrrrrr write: reset: $0058 reserved read: rrrrrrrr write: reset: $0059 reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 9 of 12) memory map input/output (i/o) section MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor memory map 51 $005a sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $005b sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $005c sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset: uu 000000 $005d sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $005e sci status register 2 (scs2) read: 000000bkfrpf write: reset:00000000 $005f sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: uuuuuuuu $0060 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:0000 000 $0061 adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $0062 adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $0063 adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 10 of 12) memory map technical data MC68HC908JG16 ? rev. 1.1 52 memory map freescale semiconductor $0064 to $007f unimplemented read: write: reset: $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad usb lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 0000000if15 write:rrrrrrrr reset:00000000 $fe07 reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 11 of 12) memory map input/output (i/o) section MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor memory map 53 $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 $fe0a reserved read: rrrrrrrr write: reset: $fe0b reserved read: rrrrrrrr write: reset: $fe0c break address high register (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address low register (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 12 of 12) memory map technical data MC68HC908JG16 ? rev. 1.1 54 memory map freescale semiconductor . table 2-1. vector addresses vector priority vector address vector lowest if15 $ffde adc conversion co mplete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 $ffe2 sci transmit vector (high) $ffe3 sci transmit vector (low) if12 $ffe4 sci receive vector (high) $ffe5 sci receive vector (low) if11 $ffe6 sci error vector (high) $ffe7 sci error vector (low) if10 $ffe8 tim2 overflow vector (high) $ffe9 tim2 overflow vector (low) if9 $ffea tim2 channel 0 and 1 vector (high) $ffeb tim2 channel 0 and 1 vector (low) if8 $ffec tim2 channel 1 vector (high) $ffed tim2 channel 1 vector (low) if7 $ffee tim2 channel 0 vector (high) $ffef tim2 channel 0 vector (low) if6 $fff0 tim1 overflow vector (high) $fff1 tim1 overflow vector (low) if5 $fff2 tim1 channel 0 and 1 vector (high) $fff3 tim1 channel 0 and 1 vector (low) if4 $fff4 tim1 channel 1 vector (high) $fff5 tim1 channel 1 vector (low) if3 $fff6 tim1 channel 0 vector (high) $fff7 tim1 channel 0 vector (low) if2 $fff8 irq vector (high) $fff9 irq vector (low) if1 $fffa usb vector (high) $fffb usb vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low) MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor random-access memory (ram) 55 technical data ? MC68HC908JG16 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 introduction this section describes the 384 by tes of ram (random-access memory). 3.3 functional description addresses $0080 through $0 1ff are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64k-byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 128 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently acce ss all page zero ram locations. page zero ram, therefore, provides i deal locations for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. random-access memory (ram) technical data MC68HC908JG16 ? rev. 1.1 56 random-access memory (ram) freescale semiconductor during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor flash memory 57 technical data ? MC68HC908JG16 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.8.1 flash block protect regi ster . . . . . . . . . . . . . . . . . . . . . . . 64 4.9 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.9.1 variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.9.2 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.9.3 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.9.4 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2 introduction this section describes the operat ion of the embedd ed flash memory. this memory can be r ead, programmed, and er ased from a single external supply. the program and er ase operations are enabled through the use of an internal charge pump. flash memory technical data MC68HC908JG16 ? rev. 1.1 58 flash memory freescale semiconductor 4.3 functional description the flash memory consists of an array of 16,384 bytes for user memory plus a block of 48 byte s for user interrupt vectors. an erased bit reads as logic 1 an d a programmed bit r eads as a logic 0. the flash memory is block erasable. the minimu m erase block size is 512 bytes. program and erase operat ion operations are facilitated through control bits in flash control register (flcr).the address ranges for the flash memory are shown as follows: $ba00?$f9ff (user memory, 16,384 bytes) $ffd0?$ffff (user interrupt vectors, 48 bytes) programming tools are available from freescale. contact your local freescale representative for more information. note: a security feature prevents vi ewing of the flash contents. 1 addr.register name bit 7654321bit 0 $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 = unimplemented figure 4-1. flash i/ o register summary 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. flash memory flash control register MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor flash memory 59 4.4 flash control register the flash control register (flcr) controls flash program and erase operation. hven ? high voltage enable bit this read/write bit enables high vo ltage from the charge pump to the memory for either progra m or erase operation. it can only be set if either pgm=1 or erase=1 and the sequence for erase or program/verify is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit confi gures the memory for mass erase operation or block erase operation when the erase bit is set. 1 = mass erase operation selected 0 = block erase operation selected erase ? erase control bit this read/write bit confi gures the memory for erase operation. this bit and the pgm bit should not be se t to 1 at t he same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit confi gures the memory for program operation. this bit and the erase bit s hould not be set to 1 at the same time. 1 = program operation selected 0 = program operation not selected address: $fe08 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 4-2. flash cont rol register (flcr) flash memory technical data MC68HC908JG16 ? rev. 1.1 60 flash memory freescale semiconductor 4.5 flash block erase operation use the following procedure to erase a block of flash memory. a block consists of 512 consecutive byte s starting from addresses $x000, $x200, $x400, $x600, $x800, $xa00, $xc00 or $xe00. the 48-byte user interrupt vectors area also form s a block. any block within the 16k bytes user memory area ($ba 00?$f9ff) can be erased alone. note: the 48-byte user interr upt vectors, $ffd0?$ffff, cannot be erased by the block erase operation because of security reasons. mass erase is required to erase this block. 1. set the erase bit and clear the mass bit in th e flash control register. 2. write any data to any flash addr ess within the address range of the block to be erased. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time t erase (10ms). 6. clear the erase bit. 7. wait for a time, t nvh (5 s). 8. clear the hven bit. 9. after time, t rcv (1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but ot her unrelated operations may occur between the steps. flash memory flash mass erase operation MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor flash memory 61 4.6 flash mass erase operation use the following proc edure to erase the en tire flash memory: 1. set both the erase bit and the mass bit in the flash control register. 2. write any data to any flash address within the address range $ffd0?$ffff. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time t merase (200ms). 6. clear the erase bit. 7. wait for a time, t nvhl (100 s). 8. clear the hven bit. 9. after time, t rcv (1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locations c annot be performed by executing code from the flash me mory; the code must be executed from ram. while these operations must be perfo rmed in the order as shown, but other unre lated operations may occur between the steps. flash memory technical data MC68HC908JG16 ? rev. 1.1 62 flash memory freescale semiconductor 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from a ddresses $xx00, $xx40, $xx80 or $xxc0. the procedure for progr amming a row of the flash memory is outlined below: 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. write any data to any flash addr ess within the address range of the row to be programmed. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time, t pgs (10 s). 6. write data to the by te being programmed. 7. wait for time, t prog (30 s). 8. repeat steps 6 and 7 until all the bytes within the row are programmed. 9. clear the pgm bit. 10. wait for time, t nvh (5 s). 11. clear the hven bit. 12. after time, t rcv (1 s), the memory can be accessed in read mode again. this program sequence is repeated th roughout the memory until all data is programmed. note: programming and erasing of flash locations c annot be performed by executing code from the flash me mory; the code must be executed from ram. while these operations must be perfo rmed in the order as shown, but other unrelated operations may occur between the steps. do not exceed t prog maximum. see 20.14 flash memory characteristics . figure 4-3 shows a flowchart represen tation for programming the flash memory. flash memory flash program operation MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor flash memory 63 figure 4-3. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. flash memory technical data MC68HC908JG16 ? rev. 1.1 64 flash memory freescale semiconductor 4.8 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the tar get application, provis ion is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flbpr). the flb pr determines the range of the flash memory which is to be prot ected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or prog ram operations. note: when the flbpr is cleared (all 0?s) , the entire flash memory is protected from being prog rammed and erased. when all the bits are set, the entire flash memory is a ccessible for program and erase. 4.8.1 flash block protect register the flash block protect regi ster is implemented as an 8-bit i/o register. the 7 bits of the 8-bit content of th is register determine the starting location of the protected range within the flash memory. bpr[7:0] ? flash blo ck protect register bit 7 to bit 0 bpr[7:1] represent bits [15:9] of a 16-bit memory address; bits [8:0] are logic 0?s. figure 4-5. flash block protect start address address: $fe09 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 figure 4-4. flash block pr otect register (flbpr) 16-bit memory address start address of flash block protect 000000000 bpr[7:1] flash memory rom-resident routines MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor flash memory 65 bpr0 is used only for bpr[7:0] = $ff, for no block protection. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to the end of flash me mory, at $ffff. with this mechanism, the pr otect start address can be x000, x200, x400, x600, x800, xa00, xc00, or xe00 within the flash memory. examples of protect start address: 4.9 rom-resident routines rom-resident routin es can be called by a progr am running in user mode or in monitor mode (see section 9. moni tor rom (mon) ) for flash programming, erasing, and verifying. the range of t he flash memory must be unprot ected (see 4.8 flash protection ) before calling the erase or programming routine. bpr[7:0] start of address of protect range $00 to $ba the entire flash memory is protected. $bc ( 1011 1100 ) $bc00 ( 1011 1100 0000 0000) $be ( 1011 1110 ) $be00 ( 1011 1110 0000 0000) $c0 ( 1100 0000 )$c000 ( 1100 0000 0000 0000) $c2 ( 1100 0010 )$c200 ( 1100 0010 0000 0000) and so on... $fe $ffd0?$ffff (user vectors) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff. table 4-1. rom-resident routines routine name call address description verify $fc03 flash verify routine erase $fc06 flash mass or block erase routine program $fc09 flash program routine flash memory technical data MC68HC908JG16 ? rev. 1.1 66 flash memory freescale semiconductor 4.9.1 variables the rom-resident r outines use three vari ables: ctrlbyt, cpuspd and laddr; and one data buffer. the minimum si ze of the data buffer is one byte and the maxi mum size is 64 bytes. cpuspd must be set befo re calling the erase or programming routines, and should be set to four times the va lue of the cpu in ternal bus speed in mhz. for example: for cpu speed of 6m hz, cpuspd should be set to 24. 4.9.2 erase routine the erase routine erases the entire or a block of flash memory. the routine does not check for a blank range before or after erase. note: a block erase cannot be performed on the last block of flash memory (user vector at $ffd0)?$ffff). table 4-2. summary of flash routine variables variable address description ctrlbyt $0088 control byte for setting mass or block erase. cpuspd $0089 timing adjustment for different cpu speeds. laddr $008a?$008b last flash address to be programmed. databuf $0100?$013f data buffer for programming and verifying. table 4-3. erase routine routine erase calling address $fc06 stack use 5 bytes input cpuspd ? cpu speed hx ? contains any address in the range to be erased ctrlbyt ? mass or block erase mass erase if bit 6 = 1 block erase if bit 6 = 0 flash memory rom-resident routines MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor flash memory 67 4.9.3 program routine the program routine pr ograms a range of addresses in flash memory, which does no t have to be on page boundaries, either at the begin or end address. 4.9.4 verify routine the verify routine reads and veri fies a range of flash memory. table 4-4. program routine routine program calling address $fc09 stack use 7 bytes input cpuspd ? cpu speed hx ? flash start address to be programmed laddr ? flash end address to be programmed databuf ? contains the data to be programmed table 4-5. verify routine routine verify calling address $fc03 stack use 6 bytes input hx ? flash start address to be verified laddr ? flash end address to be verified databuf ? contains the data to be verified output c bit ? c bit is set if verify passes databuf ? contains the data in the range of the flash memory flash memory technical data MC68HC908JG16 ? rev. 1.1 68 flash memory freescale semiconductor MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor configuration register (config) 69 technical data ? MC68HC908JG16 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 5.2 introduction this section describes the config uration register , config. the configuration register enables or disables these options: low voltage inhibit (l vi) module control and voltage trip point selection usb reset stop mode recovery time (2048 or 4096 oscdclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 oscdclk cycles) stop instruction computer operating pr operly module (cop) 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be wri tten once after each reset. all of the configuration register bits are clea red during reset. since the various options affect the operat ion of the mcu, it is recommended that this register be written immedi ately after reset. the conf iguration register is located at $001f. the configuration register may be read at anytime. configuration register (config) technical data MC68HC908JG16 ? rev. 1.1 70 configuration register (config) freescale semiconductor 5.4 configuration register lvidr ? lvi disable bit for v reg lvidr disables the lvi circuit for v reg . (see section 18. low- voltage inhibit (lvi) .) 1 = lvi circuit for v reg disabled 0 = lvi circuit for v reg enabled note: there is no lvi circuit for v rega . lvi5or3 ? lvi trip point voltage select bit for v dd lvi5or3 selects the trip point voltage of the lv i circuit for v dd . (see section 18. low-vol tage inhibit (lvi) .) 1 = lvi trips at 3.3v 0 = lvi trips at 2.4v urstd ? usb reset disable bit urstd disables the usb reset signal generating an internal reset to the cpu and internal regi sters. instead, it wil l generate an interrupt request to the cpu. (see section 11. universal serial bus module (usb) .) 1 = usb reset generates a usb interrupt request to cpu 0 = usb reset generat es a chip reset lvid ? lvi dis able bit for v dd lvid disables the lvi circuit for v dd . (see section 18. low-voltage inhibit (lvi) .) 1 = lvi circuit for v dd disabled 0 = lvi circuit for v dd enabled address: $001f bit 7654321bit 0 read: lvidr lvi5or3 urstd lvid ssrec coprs stop copd write: reset: 0* 0* 0* 0* 0 0 0 0 * lvidr, lvi5or3, urstd, and lvid bits are rese t by por (power-on reset) or lvi reset only. figure 5-1. configurat ion register (config) configuration register (config) configuration register MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor configuration register (config) 71 ssrec ? short stop recovery bit ssrec enables the cp u to exit stop mode with a delay of 2048 oscdclk cycles instead of a 4096 oscdclk cycle delay. 1 = stop mode recovery after 2048 oscdclk cycles 0 = stop mode recovery after 4096 oscdclk cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal oscillator, do not set the ssrec bit. coprs ? cop rate select bit coprs selects the cop timeout pe riod. reset clears coprs. (see section 17. computer o perating properly (cop) .) 1 = cop timeout period is 2 13 ? 2 4 oscdclk cycles 0 = cop timeout period is 2 18 ? 2 4 oscdclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 17. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled configuration register (config) technical data MC68HC908JG16 ? rev. 1.1 72 configuration register (config) freescale semiconductor MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 73 technical data ? MC68HC908JG16 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 74 central processor unit (c pu) freescale semiconductor 6.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (freescale document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.3 features feature of the cpu include: object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-re gister manipulation instructions 6-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressing range beyond 64-kbytes low-power stop and wait modes central processor unit (cpu) cpu registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 75 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map. figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 76 central processor unit (c pu) freescale semiconductor 6.4.2 index register the 16-bit index register allows i ndexed addressing of a 64k-byte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) central processor unit (cpu) cpu registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 77 note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc) central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 78 central processor unit (c pu) freescale semiconductor 6.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-car ry (add) or add- with-carry (adc) operat ion. the half-carry flag is required for binary- coded decimal (bcd) ar ithmetic operations. the daa in struction uses the states of the h and c fl ags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset: x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) central processor unit (cpu) cpu registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 79 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cpu registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipulation pr oduces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 80 central processor unit (c pu) freescale semiconductor c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of th e accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/l ogic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (freescale document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock. central processor unit (cpu) cpu during break interrupts MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 81 6.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock. after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if the break module is enabled, a br eak interrupt causes the cpu to execute the software inte rrupt instruction (swi) at the completion of the current cpu instruction. (see section 19. break module (brk) .) the program counter vectors to $fff c?$fffd ($fefc?$fefd in monitor mode). a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary table 6-1 provides a summary of t he m68hc08 instruction set. 6.9 opcode map the opcode map is provided in table 6-2 . central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 82 central processor unit (c pu) freescale semiconductor table 6-1. instruction se t summary (sheet 1 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c central processor unit (cpu) opcode map MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 83 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 table 6-1. instruction se t summary (sheet 2 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 84 central processor unit (c pu) freescale semiconductor brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction se t summary (sheet 3 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) opcode map MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 85 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ??? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction se t summary (sheet 4 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 86 central processor unit (c pu) freescale semiconductor inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ??0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 table 6-1. instruction se t summary (sheet 5 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) opcode map MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 87 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ? ? ? ? ? ? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 table 6-1. instruction se t summary (sheet 6 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 88 central processor unit (c pu) freescale semiconductor rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction se t summary (sheet 7 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) opcode map MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 89 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressi ng mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increm ent to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 6-1. instruction se t summary (sheet 8 of 8) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) technical data MC68HC908JG16 ? rev. 1.1 90 central processor unit (cpu) freescale semiconductor table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor oscillator (osc) 91 technical data ? MC68HC908JG16 section 7. oscillator (osc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.3 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .92 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 93 7.4.2 crystal amplifier out put pin (osc1) . . . . . . . . . . . . . . . . . . 93 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 93 7.4.4 crystal output frequency signal (oscxclk). . . . . . . . . . . 93 7.4.5 clock doubler out (oscdclk) . . . . . . . . . . . . . . . . . . . . . . 93 7.4.6 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.2 introduction the oscillator circuit is designed for use with crystals or ceramic resonators. the oscillat or circuit generates the crystal clock signal, oscxclk, and passes through a clo ck doubler to produce oscdclk. this clock doubler clock is further di vided by two before being passed on to the system integration modul e (sim) for bus clock generation. figure 7-1 shows the structure of the oscillator. the oscillator requires various external components. the MC68HC908JG16 oper ates from a nomi nal 12mhz crystal, providing a 6mhz internal bus cloc k. the 12mhz clock is required for various modules, such as the usb and sci. the clock doubler clock, oscdclk, is used as the ba se clock for the cop module. oscillator (osc) technical data MC68HC908JG16 ? rev. 1.1 92 oscillator (osc) freescale semiconductor 7.3 oscillator ex ternal connections in its typical configur ation, the oscillator requires five external components. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 7-1 . this figure shows only the logical representat ion of the internal components and may not represent actual circui try. the oscillator conf iguration uses five components: crystal, x 1 (nominally 12mhz) fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (not required for 12mhz) figure 7-1. oscillator external connections the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high-frequency cr ystals. refer to the crystal manufacturer?s data for more information. c1 c2 simoscen oscdclk x1 r s * * r s can be 0 (shorted) when used with mcu from sim oscout to sim clock doubler 2 to cop, sci osc1 osc2 r b 12 mhz higher frequency crystals. refer to manufacturer?s data. oscxclk 2 to usb oscillator (osc) i/o signals MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor oscillator (osc) 93 7.4 i/o signals the following paragraphs describe the oscillator input/output (i/o) signals. 7.4.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 7.4.2 crystal amplifier output pin (osc1) the osc2 pin is the output of the crystal oscillator inverting amplifier. 7.4.3 oscillator enable signal (simoscen) the simoscen signal come s from the system int egration module (sim) and enables the oscillator. 7.4.4 crystal output frequency signal (oscxclk) oscxclk is the crystal oscillator out put signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 7-1 shows only the logical rela tion of oscxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of oscxclk is unknown and may d epend on the crystal and other external factors. also, the frequen cy and amplitude of oscxclk can be unstable at startup. 7.4.5 clock doubler out (oscdclk) oscdclk is the clock doubl er output signal. it r uns at twice the speed of the crystal (f xclk ) and comes from the clock doubler circuit. oscillator (osc) technical data MC68HC908JG16 ? rev. 1.1 94 oscillator (osc) freescale semiconductor 7.4.6 oscillator out (oscout) oscout is the divide-by-two signal after the clock doubler circuit. it runs at the same speed as os cxclk, at crystal frequency (f xclk ). this signal goes to the sim, which gener ates the mcu clocks. oscout will be divided-by-two again in the sim and results in the internal bus frequency being one half of the crystal frequency. 7.5 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 7.5.1 wait mode the wait instruction has no effect on the osci llator logic. oscxclk continues to drive to the mcu. 7.5.2 stop mode the stop instructio n disables the oscxclk output. 7.6 oscillator during break mode the oscillator continue s to drive oscxclk wh en the chip enters the break state. MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 95 technical data ? MC68HC908JG16 section 8. system integration module (sim) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 98 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.2 clock startup from po r or lvi reset . . . . . . . . . . . . . . . . . 99 8.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 99 8.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 99 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 101 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 8.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 103 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 104 8.4.2.6 universal serial bus (usb) rese t . . . . . . . . . . . . . . . . . 104 8.4.2.7 registers values after different resets. . . . . . . . . . . . . 104 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 105 8.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 106 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 106 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 110 8.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2.3 interrupt stat us register 3 . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 96 system integration module (sim) freescale semiconductor 8.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 113 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 117 8.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 118 8.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . . 119 8.2 introduction this section describes the system integration module (sim). together with the cpu, t he sim controls al l mcu activities. the sim is a system state controller that coordinates cpu and exception timing. a block diagram of the sim is shown in figure 8-1 . figure 8-2 is a summary of the sim i/o registers. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources table 8-1 shows the internal signal na mes used in this section. system integration module (sim) introduction MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 97 figure 8-1. sim block diagram table 8-1. sim module signal name conventions signal name description oscdclk clock doubler output which has twice the frequency of osc1 from the oscillator oscout the oscdclk frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = oscdclk 4 = oscxclk 2) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from osc) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock oscdclk (from osc) 2 usb reset (from usb module) lvi reset (from lvi module) vdd internal pull-up system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 98 system integration module (sim) freescale semiconductor 8.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, oscout, as shown in figure 8-3 . figure 8-3. sim clock signals addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: see note reset: 0 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad usb lvi 0 write: por:10000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read:0000000if15 write:rrrrrrrr reset:00000000 figure 8-2. sim i/o register summary 2 bus clock generators sim sim counter from osc oscout oscdclk system integration module (sim) reset and system initialization MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 99 8.3.1 bus timing in user mode , the internal bus frequency is the o scillator frequency divided by two. 8.3.2 clock startup from por or lvi reset when the power-on reset (por) modu le or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 oscdclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus cl ocks start upon completion of the timeout. 8.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interr upt, break, or rese t, the sim allows oscdclk to clock the sim counter . the cpu and perip heral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 2 048 oscdclk cycles. (see 8.7.2 stop mode .) in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 8.4 reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) illegal opcode illegal address universal serial bus module (usb) low-voltage inhi bit module (lvi) system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 100 system integration module (sim) freescale semiconductor all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clear s the sim counter (see 8.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register ( srsr). (see 8.8 sim registers .) 8.4.1 external pin reset the rst pin circuit includes an internal pullup device. pulling the asynchronous rst pin low halts all processi ng. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 oscdclk cycles, assuming t hat neither the por nor the lvi was the source of the reset. see table 8-2 for details. figure 8-4 shows the relative timing. figure 8-4. extern al reset timing table 8-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l oscout system integration module (sim) reset and system initialization MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 101 8.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 oscdclk cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be assert ed for an additional 32 cycles. (see figure 8-5 .) an internal reset can be c aused by an illegal address, illegal opcode, cop timeout, lvi, t he usb module or por. (see figure 8-6 . sources of internal reset .) note: for lvi or por resets, the si m cycles through 4096 oscdclk cycles during which the si m forces the rst pin low. the internal reset signal then follows the sequence fr om the falling edge of rst shown in figure 8-5 . figure 8-5. inter nal reset timing the cop reset is asynchro nous to the bus clock. figure 8-6. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high oscdclk illegal address rst illegal opcode rst coprst por internal reset lvi usb system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 102 system integration module (sim) freescale semiconductor 8.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 oscdclk cycles. sixty- four oscdclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the foll owing events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscill ator to drive oscdclk. internal clocks to the cpu and m odules are held i nactive for 4096 oscdclk cycles to allow stab ilization of t he oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. figure 8-7. por recovery porrst osc1 oscdclk oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff system integration module (sim) reset and system initialization MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 103 8.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears the cop counter and stages 12 through 5 of the sim counter. the sim counter output, which occurs at least every 2 12 ? 2 4 oscdclk cycles, drives the cop counter. the cop should be serviced as s oon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor m ode. the cop modul e can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents t he cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. 8.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. if the stop enable bit, st op, in the mask option regi ster is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.4 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the si m reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim acti vely pulls down the rst pin for all internal reset sources. system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 104 system integration module (sim) freescale semiconductor 8.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit m odule (lvi) asserts its output to the sim when the v dd or v reg voltage falls to t he lvi reset voltage, v trip . the lvi bit in the sim reset status re gister (srsr) is set, an d the external reset pin (rst ) is held low while the sim counter counts out 4096 oscdclk cycles. sixty-four oscdclk cycles late r, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.6 universal serial bus (usb) reset the usb module will de tect a reset signaled on t he bus by the presence of an extended se0 at t he usb data pins of a device. the mcu seeing a single-ended 0 on its usb data inputs for more than 2.5 s treats that signal as a reset. after the reset is removed, the device will be in the attached, but not yet addressed or conf igured, state (refer to section 9.1 usb devices of the universal serial bus s pecification rev. 2.0 ). the device must be able to accept t he device address via a set_address command (refer to se ction 9.4 of the universal serial bus specification rev. 2.0 ) no later than 10ms after the reset is removed. usb reset can be disabled to generat e an internal reset. it can be configured to generate irq interrupt. (see section 5. configuration register (config) .) note: usb reset is disabled when the usb module is disabled by clearing the usben bit of t he usb address register (uaddr). 8.4.2.7 registers values after different resets some registers are reset by por or lvi reset only. table 8-3 shows the registers or register bits which are unaffect ed by normal resets. system integration module (sim) sim counter MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 105 8.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescaler for the computer operati ng properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the cl ock for the cop module. the sim counter is clo cked by the falli ng edge of oscdclk. 8.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. table 8-3. registers not affected by normal reset bits registers after reset (except por or lvi) after por or lvi lvidr, lvi5or3, urstd, lvid config unaffected 0 usben uaddr unaffected 0 pullen ucr3 unaffected 0 all usr0, usr1 unaffected indeterminate all ue0d0?ue0d7 unaffected indeterminate all ue1d0?ue1d7 unaffected indeterminate all ue2d0?ue2d7 unaffected indeterminate all pta, ptb, ptc, ptd, and pte unaffected indeterminate ddra7 ddra unaffected 0 system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 106 system integration module (sim) freescale semiconductor 8.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register (c onfig). if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 oscdclk cycles down to 2048 oscdclk cycles. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssre c cleared in the configur ation register (config). 8.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 8.7.2 stop mode for details.) the sim counter is free -running after all re set states. (see 8.4.2 active resets from internal sources for counter control and internal reset re covery sequences.) 8.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 8.6.1 interrupts an interrupt temporarily changes th e sequence of program execution to respond to a parti cular event. figure 8-8 flow charts the handling of system interrupts. system integration module (sim) exception control MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 107 figure 8-8. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? usb interrupt? irq interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 108 system integration module (sim) freescale semiconductor interrupts are latched and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced or the i bit is cleared. at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 8-9 shows interrupt entry timing. figure 8-10 shows interrupt recovery timing. figure 8-9 . interrupt entry figure 8-10. in terrupt recovery module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[15:8] pc ? 1 [7:0] opcode operand i bit system integration module (sim) exception control MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 109 8.6.1.1 hardware interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 8-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 8-11 . interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 110 system integration module (sim) freescale semiconductor 8.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc?1, as a har dware interrupt does. 8.6.2 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 8-4 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. 8.6.2.1 interrupt status register 1 if6?if1 ? interrupt flags 6?1 these flags indicate the presence of interrupt r equests from the sources shown in table 8-4 . 1 = interrupt request present 0 = no interrupt request present bit 1 and bit 0 ? always read 0 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r=reserved figure 8-12. interrupt st atus register 1 (int1) system integration module (sim) exception control MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 111 table 8-4. interrupt sources source flags mask (1) int register flag priority (2) vector address reset none none none 0 $fffe?$ffff swi instruction none none none 0 $fffc?$fffd usb reset interrupt rstf urstd if1 1 $fffa?$fffb usb endpoint 0 transmit txd0f txd0ie usb endpoint 0 receive rxd0f rxd0ie usb endpoint 1 transmit txd1f txd1ie usb endpoint 2 transmit txd2f txd2ie usb endpoint 2 receive rxd2f rxd2ie usb end of packet eopf eopie usb resume interrupt resumf ? irq interrupt (irq , pte4) irqf, pte4if imask if2 2 $fff8?$fff9 tim 1 channel 0 ch0f ch0ie if3 3 $fff6?$fff7 tim 1 channel 1 ch1f ch1ie if4 4 $fff4?$fff5 tim 1 channel 0 & 1 ch0f & ch1f ch01ie if5 5 $fff2?$fff3 tim 1 overflow tof toie if6 6 $fff0?$fff1 tim 2 channel 0 ch0f ch0ie if7 7 $ffee?$ffef tim 2 channel 1 ch1f ch1ie if8 8 $ffec?$ffed tim 2 channel 0 & 1 ch0f & ch1f ch01ie if9 9 $ffea?$ffeb tim 2 overflow tof toie if10 10 $ffe8?$ffe9 sci receiver overrun or orie if11 11 $ffe6?$ffe7 sci noise fag nf neie sci framing error fe feie sci parity error pe peie sci receiver full scrf scrie if12 12 $ffe4?$ffe5 sci input idle idle ilie sci transmitter empty scte sctie if13 13 $ffe2?$ffe3 sci transmission complete tc tcie keyboard interrupt keyf imaskk if14 14 $ffe0?$ffe1 adc conversion complete co co aien if15 15 $ffde?$ffdf notes : 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. 2. highest priority = 0. system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 112 system integration module (sim) freescale semiconductor 8.6.2.2 interrupt status register 2 if14?if7 ? interr upt flags 14?7 these flags indicate the presence of interrupt r equests from the sources shown in table 8-4 . 1 = interrupt request present 0 = no interrupt request present 8.6.2.3 interrupt status register 3 if15 ? interrupt flag 15 this flag indicates the presence of interrupt requests from the source shown in table 8-4 . 1 = interrupt request present 0 = no interrupt request present bit 7 to bit 1 ? always read 0 address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r=reserved figure 8-13. interrupt st atus register 2 (int2) address: $fe06 bit 7654321bit 0 read: 0000000if15 write:rrrrrrrr reset:00000000 r=reserved figure 8-14. interrupt st atus register 3 (int3) system integration module (sim) exception control MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 113 8.6.3 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 8.6.4 break interrupts the break module can st op normal program flow at a software- programmable break point by asserti ng its break interrupt output. (see section 19. break module (brk) .) the sim puts the cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 8.6.5 status flag protection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in the break flag contro l register (bfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mo de without losing stat us flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a 2- step clearing mechanism ? for example, a read of one register followed by the read or write of a nother ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 114 system integration module (sim) freescale semiconductor 8.7 low-power modes executing the wait or stop instruction puts t he mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of eac h of these mode s is described here. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 8.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 8-15 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the configuration register (config) is logic 0, then the co mputer operating properly module (cop) is enabled and remains active in wait mode. figure 8-15. wait mode entry timing figure 8-16 and figure 8-17 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction system integration module (sim) low-power modes MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 115 figure 8-16. wait recovery from interrupt or break figure 8-17. wait recover y from internal reset 8.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the oscillator si gnals (oscout and oscdclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configurati on register (config). if ssrec is set, stop recovery is r educed from the nor mal delay of 4096 oscdclk cycles down to 2048. this is ideal for applications using canned oscillators that do not require long start up times from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 oscdclk 32 cycles 32 cycles system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 116 system integration module (sim) freescale semiconductor a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the sim break st atus register (sbsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 8-18 shows stop mode entry timing. note: to minimize stop current, all pins configured as i nputs should be driven to a logic 1 or logic 0. figure 8-18. stop mode entry timing figure 8-19. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction oscdclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period system integration module (sim) sim registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 117 8.8 sim registers the sim has three memory mapped registers. sim break status register (sbsr) sim reset status register (srsr) sim break flag con trol register (sbfcr) 8.8.1 sim break status register (sbsr) the sim break status register contains a flag to indica te that a break caused an exit from st op or wait mode. sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi routi ne. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of th is. writing 0 to the sbsw bit clears it. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note 1 reset: 0 note 1. writing a logic 0 clears sbsw. r = reserved figure 8-20. sim break st atus register (sbsr) system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 118 system integration module (sim) freescale semiconductor 8.8.2 sim reset status register (srsr) this register contains sev en flags that show the sour ce of the last reset. all flag bits are cleared aut omatically following a r ead of the register. the register is initialized on power-up as shown with the por bit set and all other bits cleared. however, during a por or any other internal reset, the rst pin is pulled low. after the pin is released, it will be sampled 32 oscdclk cycles later. if th e pin is not above a v ih at that time, then the pin bit in the srsr may be set in addi tion to whatever ot her bits are set. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad usb lvi 0 write: por:10000000 = unimplemented figure 8-21. sim reset status register (srsr) system integration module (sim) sim registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 119 pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr usb ? universal serial bus reset bit 1 = last reset caused by the usb module 0 = por or read of srsr lvi ? low voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr 8.8.3 sim break flag control register (sbfcr) the sim break flag control r egister contains a bit that enables software to clear status bits while the mcu is in a break state. address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 8-22. sim break flag c ontrol register (sbfcr) system integration module (sim) technical data MC68HC908JG16 ? rev. 1.1 120 system integration module (sim) freescale semiconductor bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 121 technical data ? MC68HC908JG16 section 9. monitor rom (mon) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.4.3 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.4.4 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 9.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.5.1 extended security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single- wire interface with host com puter. this mode is also used for programming and erasing of flash memory in the mcu. monitor mode entry can be achieved without use of the higher voltage, v tst , as long as vector addresses $fffe and $ffff ar e blank, thus reducing the hardware requirement s for in-circuit programming. monitor rom (mon) technical data MC68HC908JG16 ? rev. 1.1 122 monitor rom (mon) freescale semiconductor 9.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory progr amming interface 1,472 bytes monitor rom code size monitor mode entry wi thout high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v tst , is applied to irq 9.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 9-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute host-co mputer code in ram while most mcu pins retain norm al operating mode func tions. all communication between the host computer and the m cu is through the pta0 pin. a level-shifting and multiplexing in terface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pull-up resistor. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. monitor rom (mon) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 123 figure 9-1. monitor mode circuit + + + + 10m ? mc145407 mc74hc125 hc908jg16 rst irq osc1 osc2 v ss pta0 v dd 10 k ? 10k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 12mhz 5 6 pta1 v dd 0.1 f v dd pta2 v dd 10 k ? pta3 v dd 10 k ? 10 k ? sw1 a b v tst sw2 e f (see note 2) notes: 1. affects high voltage entry to monitor mode only (sw2 at position c): sw1: position a ? bus clock = f xclk 2 sw1: position b ? bus clock = f xclk 2. sw2: position c ? high-voltage entry to monitor mode. sw2: position d ? low-voltage entry to monitor mode (with blank reset vector). see section 20. for irq voltage level requirements. 3. sw3: position e ? osc1 directly driven by exter nal oscillator. sw3: position f ? osc1 driven by crystal oscillator circuit. 10k ? v dd v dd (see note 3) (see note 1) e f c d 12mhz sw3 f xclk v reg 4.7 f 0.1 f + pte3 v dd 10 k ? monitor rom (mon) technical data MC68HC908JG16 ? rev. 1.1 124 monitor rom (mon) freescale semiconductor 9.4.1 entering monitor mode table 9-1 shows the pin conditions fo r entering monitor mode. as specified in the table, monitor mode may be ente red after a por and will allow communication at 19200 baud provided one of the following sets of conditions is met: 1. if irq = v tst : ? external clock on osc1 is 12mhz ? pta3 = high ? pte3 = high 2. if $fffe & $ffff is blank (contains $ff): ? external clock on osc1 is 12mhz ?irq = v dd ? pte3 = high table 9-1. mode entry requirements and options irq $fffe and $ffff pte3 pta3 (1) pta2 pta1 pta0 external clock, f xclk bus frequency, f bus comments v tst (2) x 1 0 0 1 1 12 mhz 12 mhz (f xclk ) high-voltage entry to monitor mode. 38400 baud communication on pta0. cop disabled. v tst (2) x 11011 12mhz 6mhz (f xclk 2) high-voltage entry to monitor mode. 19200 baud communication on pta0. cop disabled. v dd blank (contain $ff) 1xxx1 12mhz 6mhz (f xclk 2) low-voltage entry to monitor mode. 19200 baud communication on pta0. cop disabled. v dd not blank 1xxxx 12mhz 6mhz (f xclk 2) enters user mode. if $fffe and $ffff is blank, mcu will encounter an illegal address reset. notes : 1. pta3 = 0: bypasses the divide-by -two prescaler to sim when using v tst for monitor mode entry. 2. see section 20. electrical specifications for v tst voltage level requirements. factory use only monitor rom (mon) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 125 if v tst is applied to irq and pta3 is low upon monitor mode entry ( table 9-1 condition set 1), the bus frequen cy is a equal to the external clock, f xclk . if pta3 is high with v tst applied to irq upon monitor mode entry ( table 9-1 condition set 2), the bus frequen cy is a divide-by-two of the external clock. holding the pta3 pin low when entering monitor mode causes a bypass of a divide-by-two stag e at the oscillator only if v tst is applied to irq . in this event, the osco ut frequency is equal to the oscdclk frequency. entering monitor mode with v tst on irq , the cop is disabled as long as v tst is applied to either the irq or the rst . (see section 8. system integration module (sim) for more information on modes of operation.) if entering monito r mode without high voltage on irq and reset vector being blank ($fffe and $ffff) ( table 9-1 condition set 3, where irq applied voltage is v dd ), then all port a pin re quirements and conditions, including the pta3 frequen cy divisor selection, are not in effect. this is to reduce circuit require ments when performing in -circuit programming. entering monitor mode with the reset vector bei ng blank, the cop is always disabled regardles s of the state of irq or the rst . figure 9-2. low-voltage mo nitor mode entry flowchart is vector blank? por triggered? normal user mode monitor mode execute monitor code no no yes yes por reset monitor rom (mon) technical data MC68HC908JG16 ? rev. 1.1 126 monitor rom (mon) freescale semiconductor figure 9-2 . shows a simplified diagram of the monitor mode entry when the reset vector is blank and irq = v dd . an external clock of 12mhz is required for a baud rate of 19200. enter monitor mode with the pi n configuration shown in figure 9-1 by pulling rst low and then high. t he rising edge of rst latches monitor mode. once monitor mode is latched, the values on the specified pins can change. once out of reset, t he mcu waits for the host to send eight security bytes. (see 9.5 security .) after the security bytes, the mcu sends a break signal (10 consecutiv e logic zeros) to the host, indicating that it is ready to receive a command. the br eak signal also pr ovides a timing reference to allow t he host to determine t he necessary baud rate. in monitor mode, the mcu uses different ve ctors for reset, swi (software interrupt), and break interr upt than those fo r user mode. the alternate vectors are in the $f e page instead of the $ff page and allow code execution from the internal moni tor firmware instead of user code. table 9-2 is a summary of the vector differences between user mode and monitor mode. table 9-2. monitor mode vector differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) notes : 1. if the high voltage (v tst ) is removed from the irq pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. $fefe $feff $fefc $fefd $fefc $fefd monitor rom (mon) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 127 9.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. trans mit and receive baud rates must be identical. figure 9-3. monitor data format 9.4.3 break signal a start bit (logic 0) foll owed by nine logic 0 bits is a break signal. when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits and t hen echoes back the break signal. figure 9-4. br eak transaction 9.4.4 baud rate the communication baud rate is dependa nt on oscillator frequency, f xclk . the state of pta3 also affects ba ud rate if entry to monitor mode is by irq =v tst . when pta3 is hi gh, the divide by ra tio is 625. if the pta3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 312. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo table 9-3. monitor baud rate selection monitor mode entry by: oscillator clock frequency, f clk pta3 baud rate irq = v tst 12 mhz 0 38400 bps 12 mhz 1 19200 bps blank reset vector, irq = v dd 12 mhz x 19200 bps monitor rom (mon) technical data MC68HC908JG16 ? rev. 1.1 128 monitor rom (mon) freescale semiconductor 9.4.5 commands the monitor rom uses t he following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit del ay at the end of each command allows the host to send a break c haracter to cancel the command. a delay of two bit times occurs bef ore each echo and before read, iread, or read sp data is returned. the dat a returned by a read command appears after the echo of t he last byte of the command. note: wait one bit ti me after each echo befor e sending the next byte. figure 9-5. read transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, 2 bit times monitor rom (mon) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 129 figure 9-6. write transaction a brief description of each moni tor mode command is given in table 9-4 through table 9-9 . table 9-4. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, 2 bit times read read echo sent to monitor address high address high address low data return address low monitor rom (mon) technical data MC68HC908JG16 ? rev. 1.1 130 monitor rom (mon) freescale semiconductor table 9-5. write (write memory) command description write byte to memory operand specifics 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence table 9-6. iread (i ndexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence write write echo semt to monitor address high address high address low address low data data iread iread echo sent to monitor data return data monitor rom (mon) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 131 note: a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64k-byte memory map. table 9-7. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence iwrite iwrite echo sent to monitor data data table 9-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence readsp readsp echo sent to monitor sp return sp high low monitor rom (mon) technical data MC68HC908JG16 ? rev. 1.1 132 monitor rom (mon) freescale semiconductor the mcu executes the swi and pshh instructio ns when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instructions. before sendi ng the run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command return s the incremented st ack pointer value, sp + 1. the high and low bytes of t he program counter are at addresses sp + 5 and sp + 6. figure 9-7. stack pointer at monitor mode entry table 9-9. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 monitor rom (mon) security MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 133 9.5 security a security feature discourages unaut horized reading of flash locations while in monitor mode. the host can bypass the securi ty feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locati ons $fff6?$fffd contain user- defined data. note: do not leave locati ons $fff6?$fffd blank . for security reasons, program locations $fff6?$fffd. during monitor mode entry, the mcu waits after the power-on reset for the host to send th e eight security bytes on pi n pta0. if the received bytes match those at location s $fff6?$fffd, the hos t bypasses the security feature and can read al l flash locations and execute code from flash. security remains by passed until a power-on or an lvi reset occurs. if the rese t was not a power-on or an lvi reset, security remains bypassed and security code entry is not required. (see figure 9-8 .) figure 9-8. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pta0 rst v dd 4096 + 32 oscdclk cycles 256 bus cycles (minimum) 1 4 1 1 2 1 break notes: 2 = data return delay, 2 bit times. 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times. monitor rom (mon) technical data MC68HC908JG16 ? rev. 1.1 134 monitor rom (mon) freescale semiconductor upon power-on reset, if the receiv ed bytes of the se curity code do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remain s in monitor mode, but reading a flash location returns an invalid val ue and trying to exec ute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mc u transmits a br eak character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character unti l after the host sends the eight security bytes. to determine whether the security c ode entered is correct, check to see if bit 6 of ram address $ 80 is set. if it is, then the correct security code has been entered and fl ash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to atte mpt another entry. after failing the security s equence, the flash modul e can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operat ion clears the security code locations so that all eight security bytes become $ff (blank). 9.5.1 extended security to further disable moni tor mode functions, the monitor commands can be disabled by writing $7b to th e flash location $ffd1 and $87 to the flash location $ffd0. table 9-10 shows the security settings that affect monitor mode operations. table 9-10. monitor mode security extended security monitor mode entry security monitor commands available not set bypassed read/write of ram and flash. failed read/write of ram. read of flash disabled. flash can only be mass erased. set bypassed read/write of ram and flash disabled. failed read/write of ram. read of flash disabled. flash can only be mass erased. MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 135 technical data ? MC68HC908JG16 section 10. timer interface module (tim) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 142 10.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .143 10.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 143 10.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 144 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 145 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.9.1 tim clock pin (pte0/tc lk) . . . . . . . . . . . . . . . . . . . . . . .149 10.9.2 tim channel i/o pins (pte 1/t1ch01:pte2/t2ch01) . . . 149 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 150 10.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.10.3 tim counter modulo r egisters . . . . . . . . . . . . . . . . . . . . . 153 10.10.4 tim channel status and control registers . . . . . . . . . . . . 154 10.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 136 timer interface module (tim) freescale semiconductor 10.2 introduction this section describes the timer in terface (tim) modul e. the tim is a two-channel timer that provides a timing refere nce with input capture, output compare, and pulse-wid th-modulation functions. figure 10-1 is a block diagram of the tim. this particular mcu has tw o timer interface modul es which are denoted as tim1 and tim2. note: tim1 and tim2 each have channel 0 and channel 1 i/os connected together, forming a comm on i/o. because of th is common i/o, both channels should not be simultaneously configured for output compare functions, otherwise, port pin contention will occur. 10.3 features features of the tim include: two input capture/ou tput compare channels on one common i/o: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse- width-modulation (pwm) signal generation programmable tim clock input ? 7-frequency internal bus cl ock prescaler selection ? external tim clock input (bus frequency 2 maximum) free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits timer interface module (tim) pin name conventions MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 137 10.4 pin name conventions the text that follows describes bot h timers, tim1 and tim2. the tim input/output (i/o) pin names are t[ 1,2]ch01 (timer channel 01), where ?1? is used to indicate tim1 and ?2 ? is used to indica te tim2. the two tims share two i/o pins with two i/ o port pins. the full names of the tim i/o pins are listed in table 10-1 . the generic pin na mes appear in the text that follows. note: references to either timer 1 or time r 2 may be made in the following text by omitting the timer number. for exam ple, tch01 may refer generically to t1ch01 and t2ch01. 10.5 functional description figure 10-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. channel 0 and channel 1 i/os ar e connected toget her, forming a common i/o. although the two tim channel s are programmable independently as input capt ure channels, the input c apture signal will be the same for both channels. output compare functions should only be enabled for one channel to avoid i/o contention. table 10-1. pin name conventions tim generic pin names: t[1,2]ch01 tclk full tim pin names: tim1 pte1/t1ch01 pte0/tclk tim2 pte2/t2ch01 timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 138 timer interface module (tim) freescale semiconductor figure 10-1. tim block diagram figure 10-2 summarizes the timer registers. note: references to either timer 1 or time r 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock t[1,2]ch01 interrupt logic port logic interrupt logic interrupt logic port logic tclk ch01ie els0b els0a ms0a els0b els0a ms0a timer interface module (tim) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 139 addr.register name bit 7654321bit 0 $000a timer 1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000c timer 1 counter register high (t1cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $000d timer 1 counter register low (t1cntl) read: bit 7 654321bit 0 write: reset:00000000 $000e timer 1 counter modulo register high (t1modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $000f timer 1 counter modulo register low (t1modl) read: bit 7654321bit 0 write: reset:11111111 $0010 timer 1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 timer 1 channel 0 register high (t1ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0012 timer 1 channel 0 register low (t1ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0013 timer 1 channel 1 status and control register (t1sc1) read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 10-2. tim i/o regist er summary (sheet 1 of 3) timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 140 timer interface module (tim) freescale semiconductor $0014 timer 1 channel 1 register high (t1ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0015 timer 1 channel 1 register low (t1ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0040 timer 2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0042 timer 2 counter register high (t2cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0043 timer 2 counter register low (t2cntl) read: bit 7 654321bit 0 write: reset:00000000 $0044 timer 2 counter modulo register high (t2modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0045 timer 2 counter modulo register low (t2modl) read: bit 7654321bit 0 write: reset:11111111 $0046 timer 2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0047 timer 2 channel 0 register high (t2ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 10-2. tim i/o regist er summary (sheet 2 of 3) timer interface module (tim) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 141 10.5.1 tim counter prescaler the tim clock source can be one of th e seven prescaler outputs or the tim clock pin, pte0/tclk. the pre scaler generates seven clock rates from the internal bus cl ock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc ) select the tim clock source. 10.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. $0048 timer 2 channel 0 register low (t2ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0049 timer 2 channel 1 status and control register (t2sc1) read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $004a timer 2 channel 1 register high (t2ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $004b timer 2 channel 1 register low (t2ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 10-2. tim i/o regist er summary (sheet 3 of 3) timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 142 timer interface module (tim) freescale semiconductor 10.5.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 10.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow perio d. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. timer interface module (tim) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 143 10.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enabl es the tim channel 1 registers to synchronously control t he output after the tim overflows. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the output are the ones writte n to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 10.5.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 10-3 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic 1. program the tim to set the pi n if the state of the pwm pulse is logic 0. timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 144 timer interface module (tim) freescale semiconductor the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is $000. see 10.10.1 tim status and control register . figure 10-3. pwm peri od and pulse width the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128 /256 or 50%. 10.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 10.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface module (tim) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 145 use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger val ue in an output compare interrupt routine (at the end of the current pulse) c ould cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 10.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel re gisters of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writ ing to the tim channel 1 registers enables the ti m channel 1 registers to synchronously control the pulse width at t he beginning of the nex t pwm period. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the pulse width are the ones written to last. tsc0 c ontrols and monitors the buffered pwm functi on, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a gener al-purpose i/o pin. timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 146 timer interface module (tim) freescale semiconductor note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. user so ftware should track the currently active channel to prevent writing a new value to the active channel. writing to the active c hannel registers is the same as generating unbuffer ed pwm signals. 10.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter and pre scaler by setting the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 10-3 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 10-3 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop. timer interface module (tim) interrupts MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 147 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output. tim status contro l register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 10.10.4 tim channel status and c ontrol registers .) 10.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overfl ow interrupt enable bit, toie, enables tim overflow cpu interr upt requests. tof and toie are in the tim status and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxi e = 1. chxf and ch xie are in the tim channel x status and control register. 10.7 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 148 timer interface module (tim) freescale semiconductor 10.7.1 wait mode the tim remains active after the executi on of a wait instru ction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. 10.7.2 stop mode the tim is inactive after the executi on of a stop instru ction. the stop instruction does no t affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 10.8 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see 8.8.3 sim break flag control register (sbfcr) .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. timer interface module (tim) i/o signals MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 149 10.9 i/o signals port e shares three of its pins with the tim. pt e0/tclk is an external clock input to the tim prescaler. the two tim channel i/o pins are pte1/t1ch01 and pte2/t2ch01. 10.9.1 tim clock pin (pte0/tclk) pte0/tclk is an external clock input that can be the clock source for the tim counter instead of the presca led internal bus cl ock. select the pte0/tclk input by writing logic 1s to the three presca ler select bits, ps[2:0]. (see 10.10.1 tim status and control register .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency 2 pte0/tclk is available as a general -purpose i/o pin when not used as the tim clock input. when the pte0/t clk pin is the tim clock input, it is an input regardless of the state of the ddre0 bit in data direction register e. 10.9.2 tim channel i/o pins (pte1/t1ch01:pte2/t2ch01) each tim i/o pin is programmable independently as an input capture pin or an output compare pin, or configured as buffe red output compare or buffered pwm pins. 1 bus frequency ------------------ ------------------- t su + timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 150 timer interface module (tim) freescale semiconductor 10.10 i/o registers note: references to either timer 1 or time r 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. these i/o registers control and monitor operati on of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0, tsc1) tim channel registers (t ch0h:tch0l, tch1h:tch1l) 10.10.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock address: t1sc, $000a and t2sc, $0040 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 10-4. tim st atus and control register (tsc) timer interface module (tim) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 151 tof ? tim overflow flag bit this read/write flag is set when t he tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register w hen tof is set and then writing a logic 0 to to f. if another tim overfl ow occurs before the clearing sequence is co mplete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. rese t clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is reset and always r eads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 152 timer interface module (tim) freescale semiconductor ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 10-2 shows. reset clears the ps[2:0] bits. 10.10.2 tim counter registers the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latc hed during the break. table 10-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 tclk address: t1cnth, $000c and t2cnth, $0042 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 10-5. tim counter registers high (tcnth) timer interface module (tim) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 153 10.10.3 tim counter modulo registers the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow inte rrupts until the low byte (tmodl) is written. reset sets the ti m counter modulo registers. note: reset the tim counter bef ore writing to the tim counter modulo registers. address: t1cntl, $000d and t2cntl, $0043 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = unimplemented figure 10-6. tim counte r registers low (tcntl) address: t1modh, $000e and t2modh, $0044 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 10-7. tim counter mo dulo register high (tmodh) address: t1modl, $000f and t2modl, $0045 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 10-8. tim counter m odulo register low (tmodl) timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 154 timer interface module (tim) freescale semiconductor 10.10.4 tim channel status and control registers each of the tim channel st atus and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 0% and 1 00% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. address: t1sc0, $0010 and t2sc0, $0046 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 10-9. tim channel 0 stat us and control register (tsc0) address: t1sc1, $0013 and t2sc1, $0049 bit 7654321bit 0 read: ch1f ch1ie ch01ie ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 10-10. tim channel 1 stat us and control register (tsc1) timer interface module (tim) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 155 when tim cpu interrupt requests ar e enabled (chxie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled ch01ie ? ch0f and ch1f interrupt enable bit this read/write bit enabl es tim cpu interrupt service requests when ch0f and ch1f are set. reset clears the ch01ie bit. 1 = cpu interrupt requests when ch0f and ch1f are set 0 = no cpu interrupt requests when ch0f and ch1f are set ms0b ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. ms0b exists only in the tim1 c hannel 0 and tim2 c hannel 0 status and control registers. setting ms0b disables the channel 1 status and c ontrol register. reset clears the ms0b bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa 0:0, this read/write bi t selects either input capture operation or unbuffered output compare/pwm operation. see table 10-3 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 156 timer interface module (tim) freescale semiconductor when elsxb:elsxa = 0:0, this read/wr ite bit selects the initial output level of the tchx pin. see table 10-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register. elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 10-3 shows how elsxb and elsx a work. reset clears the elsxb and elsxa bits. table 10-3. mode, edge, and level selection ms0b:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm (1) notes : 1. enable only one channel for unbuffered output compare or pwm functions. avoid the following configuration: ms0b = 0, ms0a = 1, ms1a = 1, and elsxb:a 00 toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare timer interface module (tim) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 157 note: before enabling a tim ch annel register for input capture operation, make sure that the tchx pin is st able for at leas t two bus clocks. tovx ? toggle on overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggle s on tim counter overflow 0 = channel x pin does not t oggle on tim counter overflow note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic 1, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 10-11 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 10-11. chxmax latency 10.10.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module (tim) technical data MC68HC908JG16 ? rev. 1.1 158 timer interface module (tim) freescale semiconductor in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. address: t1ch0h, $0011 and t2ch0h, $0047 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 10-12. tim channel 0 register high (tch0h) address: t1ch0l, $0012 and t2ch0l $0048 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 10-13. tim channel 0 register low (tch0l) address: t1ch1h, $0014 and t2ch1h, $004a bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 10-14. tim channel 1 register high (tch1h) address: t1ch1l, $0015 and t2ch1l, $004b bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 10-15. tim channel 1 register low (tch1l) MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 159 technical data ? MC68HC908JG16 section 11. universal serial bus module (usb) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.5.1 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.5.1.1 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.5.1.2 packet identifier fiel d . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.5.1.3 address field (addr) . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.1.4 endpoint field (endp) . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.1.5 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . 170 11.5.1.6 end-of-packet (eop) . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.5.2 reset signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5.3 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.5.4 resume after suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.4.1 host initiated resume . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.5.4.2 usb reset signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.5.4.3 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 11.5.5 low-speed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.6 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.7 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.2 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7.2.1 output driver charac teristics . . . . . . . . . . . . . . . . . . . . . 176 11.7.2.2 low speed (1.5 m bps) driver characterist ics . . . . . . . . 176 11.7.2.3 receiver data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.4 data source jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.2.5 data signal rise and fall time . . . . . . . . . . . . . . . . . . . 178 universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 160 universal serial bus module (usb) freescale semiconductor 11.7.3 usb control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.8.1 usb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.8.2 usb interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.8.3 usb interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.8.4 usb interrupt register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.8.5 usb control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.8.6 usb control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.8.7 usb control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.8.8 usb control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.8.9 usb control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.8.10 usb status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.8.11 usb status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.8.12 usb endpoint 0 data r egisters . . . . . . . . . . . . . . . . . . . . . 196 11.8.13 usb endpoint 1 data r egisters . . . . . . . . . . . . . . . . . . . . . 197 11.8.14 usb endpoint 2 data r egisters . . . . . . . . . . . . . . . . . . . . . 198 11.9 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.9.1 usb end-of-transaction interrupt . . . . . . . . . . . . . . . . . . . 199 11.9.1.1 receive control endpoint 0 . . . . . . . . . . . . . . . . . . . . . . 200 11.9.1.2 transmit control endpoint 0 . . . . . . . . . . . . . . . . . . . . . 202 11.9.1.3 transmit endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 11.9.1.4 transmit endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.1.5 receive endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.2 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.9.3 end-of-packet interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.2 introduction this section describes the universal serial bus (usb) module. the usb module is designed to serve as a lo w-speed (ls) usb device per the universal serial bus specification rev. 2.0 . control and interrupt data transfers are supported. endpoint 0 functions as a transmit/receive control endpoint; endpoint 1 functions as interrupt transmit endpoint; endpoint 2 functions as interrupt transmit or receive endpoint. universal serial bus module (usb) features MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 161 11.3 features features of the us b module include: universal serial bus specif ication 2.0 low-speed functions 1.5 mbps data rate on-chip 3.3v regulator endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer endpoint 1 with 8-byte transmit buffer endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer usb data control logic: ? control endpoint 0 and in terrupt endpoints 1 and 2 ? packet decoding/generation ? crc generation and checking ? nrzi (non-return-to zero inserted) enc oding/decoding ? bit-stuffing usb reset options: ? internal mcu reset generation ? cpu interrupt request generation suspend and resume operations , with remote wakeup support usb-generated interrupts: ? transaction interrupt driven ? resume interrupt ? end-of-packet interrupt ? usb reset stall, nak, and a ck handshake generation universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 162 universal serial bus module (usb) freescale semiconductor 11.4 pin name conventions the usb share two i/o pins with two port e i/o pi ns. the full name of the usb i/o pin is listed in table 11-1 . the generic pin name appear in the text that follows. table 11-1. usb module pin name conventions usb generic pin names: d+ d? full usb pin names: pte3/d+ pte4/d? addr.register name bit 7654321bit 0 $0018 usb interrupt register 2 (uir2) read: 00000000 write: eopfr rstfr txd2fr rxd2fr txd1fr resumfr txd0fr rxd0fr reset:00000000 $0019 usb control register 2 (ucr2) read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 $001a usb control register 3 (ucr3) read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 * pullen bit is reset by por or lvi reset only. $001b usb control register 4 (ucr4) read: 00000 fusbo fdp fdm write: reset:00000000 $0020 usb endpoint 0 data register 0 (ue0d0) read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t 04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset $0021 usb endpoint 0 data register 1 (ue0d1) read: ue0r17 ue0r16 ue0r15 ue0r14 ue0r13 ue0r12 ue0r11 ue0r10 write: ue0t17 ue0t16 ue0t15 ue0t 14 ue0t13 ue0t12 ue0t11 ue0t10 reset: unaffected by reset = unimplemented u = unaffected by reset figure 11-1. usb i/o regist er summary (sheet 1 of 4) universal serial bus module (usb) pin name conventions MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 163 $0022 usb endpoint 0 data register 2 (ue0d2) read: ue0r27 ue0r26 ue0r25 ue0r24 ue0r23 ue0r22 ue0r21 ue0r20 write: ue0t27 ue0t26 ue0t25 ue0t 24 ue0t23 ue0t22 ue0t21 ue0t20 reset: unaffected by reset $0023 usb endpoint 0 data register 3 (ue0d3) read: ue0r37 ue0r36 ue0r35 ue0r34 ue0r33 ue0r32 ue0r31 ue0r30 write: ue0t37 ue0t36 ue0t35 ue0t 34 ue0t33 ue0t32 ue0t31 ue0t30 reset: unaffected by reset $0024 usb endpoint 0 data register 4 (ue0d4) read: ue0r47 ue0r46 ue0r45 ue0r44 ue0r43 ue0r42 ue0r41 ue0r40 write: ue0t47 ue0t46 ue0t45 ue0t 44 ue0t43 ue0t42 ue0t41 ue0t40 reset: unaffected by reset $0025 usb endpoint 0 data register 5 (ue0d5) read: ue0r57 ue0r56 ue0r55 ue0r54 ue0r53 ue0r52 ue0r51 ue0r50 write: ue0t57 ue0t56 ue0t55 ue0t 54 ue0t53 ue0t52 ue0t51 ue0t50 reset: unaffected by reset $0026 usb endpoint 0 data register 6 (ue0d6) read: ue0r67 ue0r66 ue0r65 ue0r64 ue0r63 ue0r62 ue0r61 ue0r60 write: ue0t67 ue0t66 ue0t65 ue0t 64 ue0t63 ue0t62 ue0t61 ue0t60 reset: unaffected by reset $0027 usb endpoint 0 data register 7 (ue0d7) read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t 74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset $0028 usb endpoint 1 data register 0 (ue1d0) read: write: ue1t07 ue1t06 ue1t05 ue1t 04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset $0029 usb endpoint 1 data register 1 (ue1d1) read: write: ue1t17 ue1t16 ue1t15 ue1t 14 ue1t13 ue1t12 ue1t11 ue1t10 reset: unaffected by reset $002a usb endpoint 1 data register 2 (ue1d2) read: write: ue1t27 ue1t26 ue1t25 ue1t 24 ue1t23 ue1t22 ue1t21 ue1t20 reset: unaffected by reset $002b usb endpoint 1 data register 3 (ue1d3) read: write: ue1t37 ue1t36 ue1t35 ue1t 34 ue1t33 ue1t32 ue1t31 ue1t30 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 11-1. usb i/o regist er summary (sheet 2 of 4) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 164 universal serial bus module (usb) freescale semiconductor $002c usb endpoint 1 data register 4 (ue1d4) read: write: ue1t47 ue1t46 ue1t45 ue1t 44 ue1t43 ue1t42 ue1t41 ue1t40 reset: unaffected by reset $002d usb endpoint 1 data register5 (ue1d5) read: write: ue1t57 ue1t56 ue1t55 ue1t 54 ue1t53 ue1t52 ue1t51 ue1t50 reset: unaffected by reset $002e usb endpoint 1 data register 6 (ue1d6) read: write: ue1t67 ue1t66 ue1t65 ue1t 64 ue1t63 ue1t62 ue1t61 ue1t60 reset: unaffected by reset $002f usb endpoint 1 data register 7 (ue1d7) read: write: ue1t77 ue1t76 ue1t75 ue1t 74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset $0030 usb endpoint 2 data register 0 (ue2d0) read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t 04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset $0031 usb endpoint 2 data register 1 (ue2d1) read: ue2r17 ue2r16 ue2r15 ue2r14 ue2r13 ue2r12 ue2r11 ue2r10 write: ue2t17 ue2t16 ue2t15 ue2t 14 ue2t13 ue2t12 ue2t11 ue2t10 reset: unaffected by reset $0032 usb endpoint 2 data register 2 (ue2d2) read: ue2r27 ue2r26 ue2r25 ue2r24 ue2r23 ue2r22 ue2r21 ue2r20 write: ue2t27 ue2t26 ue2t25 ue2t 24 ue2t23 ue2t22 ue2t21 ue2t20 reset: unaffected by reset $0033 usb endpoint 2 data register 3 (ue2d3) read: ue2r37 ue2r36 ue2r35 ue2r34 ue2r33 ue2r32 ue2r31 ue2r30 write: ue2t37 ue2t36 ue2t35 ue2t 34 ue2t33 ue2t32 ue2t31 ue2t30 reset: unaffected by reset $0034 usb endpoint 2 data register 4 (ue2d4) read: ue2r47 ue2r46 ue2r45 ue2r44 ue2r43 ue2r42 ue2r41 ue2r40 write: ue2t47 ue2t46 ue2t45 ue2t 44 ue2t43 ue2t42 ue2t41 ue2t40 reset: unaffected by reset $0035 usb endpoint 2 data register 5 (ue2d5) read: ue2r57 ue2r56 ue2r55 ue2r54 ue2r53 ue2r52 ue2r51 ue2r50 write: ue2t57 ue2t56 ue2t55 ue2t 54 ue2t53 ue2t52 ue2t51 ue2t50 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 11-1. usb i/o regist er summary (sheet 3 of 4) universal serial bus module (usb) pin name conventions MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 165 $0036 usb endpoint 2 data register 6 (ue2d6) read: ue2r67 ue2r66 ue2r65 ue2r64 ue2r63 ue2r62 ue2r61 ue2r60 write: ue2t67 ue2t66 ue2t65 ue2t 64 ue2t63 ue2t62 ue2t61 ue2t60 reset: unaffected by reset $0037 usb endpoint 2 data register 7 (ue2d7) read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t 74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset $0038 usb address register (uaddr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:0*0000000 * usben bit is reset by por or lvi reset only. $0039 usb interrupt register 0 (uir0) read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 $003a usb interrupt register 1 (uir1) read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 $003b usb control register 0 (ucr0) read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 $003c usb control register 1 (ucr1) read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $003d usb status register 0 (usr0) read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset $003e usb status register 1 (usr1) read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u000uuuu addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 11-1. usb i/o regist er summary (sheet 4 of 4) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 166 universal serial bus module (usb) freescale semiconductor 11.5 functional description figure 11-2 shows the block diagram of the usb m odule. the usb module manages communications be tween the host and the usb function. the module is partitioned into three functional blocks. these blocks consist of a dual-function tran sceiver, the usb control logic, and the endpoint registers. the blocks are further detailed later in this section (see 11.7 hardware description ). figure 11-2. usb block diagram d + d ? transceiver rcv vpin vmin vpout vmout cpu bus usb registers usb upstream port usb control logic 6mhz from osc universal serial bus module (usb) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 167 11.5.1 usb protocol figure 11-3 shows the various transacti on types supported by the usb module. the transactions ar e portrayed as error free. the effect of errors in the data flow are discussed later. figure 11-3. supported tr ansaction types per endpoint setup in out data0/1 data0 data1 ack data1 out ack out data0 ack ack data0/1 endpoint 0 transactions: control write control read no-data control endpoints 1 & 2 transactions: interrupt bulk transmit in ack key: unrelated bus traffic host generated device generated ack setup out in data0/1 data0 data1 ack data1 in ack in data0 ack ack ack setup in data0 data1 ack ack data0/1 in ack universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 168 universal serial bus module (usb) freescale semiconductor each usb transaction is comprised of a series of pa ckets. the usb module supports the pa cket types shown in figure 11-4 . token packets are generated by the usb host and dec oded by the usb device. data and handshake packets are both dec oded and generat ed by the usb device, depending on the type of transaction. figure 11-4. support ed usb packet types the following sections detail each segm ent used to form a complete usb transaction. 11.5.1.1 sync pattern the nrzi bit pattern shown in figure 11-5 is used as a synchronization pattern and is prefixed to each packet. this pattern is equivalent to a data pattern of seven 0s followed by a 1 ($80). figure 11-5. s ync pattern token packet: in out sync pid pid addr endp crc5 eop setup data packet: data0 sync pid pid data crc16 eop data1 0 ? 8 bytes handshake packet: ack nak sync pid pid eop stall sync pattern pid0 pid1 idle nrzi data encoding universal serial bus module (usb) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 169 the start of a packet (sop ) is signaled by the orig inating port by driving the d+ and d? lines from the idle state (also referred to as the j state) to the opposite logi c level (also referred to as the k state). this switch in levels represents the firs t bit of the sync field. figure 11-6 shows the data signaling and voltage levels for the start of pa cket and the sync pattern. figure 11-6. sop, sync signaling, and voltage levels 11.5.1.2 packet identifier field the packet identifier field is an 8- bit number comprised of the 4-bit packet identification and its comple ment. the field follows the sync pattern and determines the direction and type of transaction on the bus. table 11-2 shows the packet identifier va lues for the supported packet types. end of sync first bit of packet sop bus idle v oh (min.) v se (max) v se (min.) v ol (min.) v ss table 11-2. supported packet identifiers packet identifier value packet identifier type %1001 in token %0001 out token %1101 setup token %0011 data0 packet %1011 data1 packet %0010 ack handshake %1010 nak handshake %1110 stall handshake universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 170 universal serial bus module (usb) freescale semiconductor 11.5.1.3 address field (addr) the address field is a 7-bit number that is used to select a particular usb device. this field is compared to the lower seven bi ts of the uaddr register to deter mine if a given transaction is targeting the mcu usb device. 11.5.1.4 endp oint field (endp) the endpoint field is a 4-bit number th at is used to select a particular endpoint within a usb devic e. for the mcu, this will be a binary number between 0 and 2 inclusive. any other value will cause the transaction to be ignored. 11.5.1.5 cyclic r edundancy check (crc) cyclic redundancy checks are used to verify the address and data stream of a usb transacti on. this field is five bi ts wide for token packets and 16 bits wide for data packets. crcs are generated in the transmitter and sent on the usb data lines after both the endpoint fi eld and the data field. 11.5.1.6 end-of-packet (eop) the single-ended 0 (se0) state is us ed to signal an end-of-packet (eop). the single- ended 0 state is indicated by both d+ and d? being below 0.8v. eop will be signaled by driving d+ and d? to the single- ended 0 state for two bit times followed by drivi ng the lines to the idle state for one bit time. the transition from the single-ended 0 to the idle state defines the end of the packet. the idle stat e is asserted for one bit time and then both the d+ and d? output drivers ar e placed in their high- impedance state. the bus termination re sistors hold the bu s in the idle state. figure 11-7 shows the data signaling and voltage levels for an end-of-packet transaction. universal serial bus module (usb) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 171 figure 11-7. eop tr ansaction voltage levels the width of the se0 in the eop is about two bit times. the eop width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines. figure 11-8. eop width timing 11.5.2 reset signaling the usb module will de tect a reset signaled on t he bus by the presence of an extended se0 at t he usb data pins of a device. the mcu seeing a single-ended 0 on its usb data inputs for more than 8 s treats that signal as a reset. a usb sourced reset will hold the mcu in reset fo r the duration of the reset on the usb bus. the us b bit in the reset st atus register (srsr) will be set after the internal reset is removed. refer to 8.8.2 sim reset status register (srsr) for more detail. the mcu?s reset recovery sequence is detailed in section 8. system int egration module (sim) . bus driven to last bit of bus idle eop strobe packet idle state bus floats v oh (min.) v se (max) v se (min.) v ol (min.) v ss eop width t period differential data lines data crossover level universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 172 universal serial bus module (usb) freescale semiconductor the reset flag bit (rst f) in the usb interrupt regi ster 1 (uir1) also will be set after the internal re set is removed. refer to 11.8.3 usb interrupt register 1 for more detail. after a reset is removed, the device will be in the def ault, but not yet addressed or configured state (refer to section 9.1 usb device states of the universal serial bus s pecification rev. 2.0 ). the device must be able to accept a device address via a set_address command (refer to section 9.4 standard device request in the universal serial bus specification rev. 2.0 ) no later than 10ms afte r the reset is removed. reset can wake a device from the suspended mode. note: usb reset can be configured not to generate a reset sign al to the cpu by setting the urstd bit of the confi guration register (see section 5. configuration register (config) ). when a usb reset is detected, the cpu generates an usb interrupt. 11.5.3 suspend the mcu supports suspend mode for low power. sus pend mode should be entered when the usb data lines are in the idle state for more than 3ms. entry into suspen d mode is controlled by the suspnd bit in the usb interrupt register . any low-speed bus ac tivity should keep the device out of the suspend state. low-speed device s are kept awake by periodic low-speed eop signals from the host. this is referred to as low speed keep alive (refer to section 11.8.4.1 low-speed keep-alive in the universal serial bus specification rev. 2.0 ). firmware should monitor the eo pf flag and enter suspend mode by setting the suspnd bi t if an eop is not detected for 3ms. per the usb specificati on, the bus powered usb system is required to draw less than 500 a from the v dd supply when in th e suspend state. this includes the current supplied by the voltage regulator to the 1.5k ? to ground termination resi stors placed at the ho st end of the usb bus. this low-current requirement means that fi rmware is responsible for entering stop mode once the usb module has been placed in the suspend state. universal serial bus module (usb) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 173 11.5.4 resume after suspend the mcu can be activated from t he suspend state by normal bus activity, a usb reset signal, or by a forced resume dr iven from the mcu. 11.5.4.1 host initiated resume the host signals resume by initiating resume signallin g (k state) for at least 20ms followed by a stan dard low-speed eop signal. this 20ms ensures that all devices in the usb network are awakened. after resuming the bus, the host mu st begin sending bus traffic within 3ms to prevent the device fr om re-entering suspend mode. 11.5.4.2 usb reset signalling reset can wake a device from the suspended mode. 11.5.4.3 remote wakeup the mcu also supports the remote wakeup feature. the firmware has the ability to exit su spend mode by signaling a resume state to the upstream host or hub. a non-idle state (k state) on the usb data lines is accomplished by asserting the fr esum bit in the ucr1 register. when using the remote wakeup capability , the firmware must wait for at least 5ms after the bus is in the id le state before se nding the remote wakeup resume signaling. this allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. the fresum bit should be asserted to cause the resume state on the usb data lines for at least 10ms, but not more than 15ms. note that the resume signalling is controlled by the fre sum bit and meeting the timing specifications is dependent on the firmware. when fresum is cleared by firmware, the da ta lines will return to their high-impedance state. refer to register definitions (see 11.8.6 usb control register 1 ) for more information about how the force resume (fresum) bit can be used to initiate the remote wakeup feature. universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 174 universal serial bus module (usb) freescale semiconductor 11.5.5 low-speed device low-speed devices are conf igured by the position of a pull-up resistor on the usb d? pin of t he mcu. low-speed device s are terminated as shown in figure 11-9 with the pull-up on the d? line. figure 11-9. external low -speed device configuration for low-speed transmissions, the tr ansmitter?s eop width must be between 1.25 s and 1.50 s. these ranges include ti ming variations due to differential buffer del ay and rise/fall time mismatches and to noise and other random effects. a low-speed re ceiver must accept a 670ns se0 followed by a j transition as a valid eop. an se0 shorter than 330ns or an se0 not followed by a j transition are rejected as an eop. any se0 that is 8 s or longer is automatically a reset. 11.6 clock requirements the low-speed data rate is nominally 1.5 mbps. the oscxclk 2 (6mhz) signal driven by t he oscillator circuits is the clock source for the usb module and requi res that a 12mhz oscill ator circuit be connected to the osc1 and osc2 pins. the permitted frequency to lerance for low- speed functions is approximately 1.5% (15,000 ppm). this tolerance includes inaccuracies from all sources: initial frequency accuracy, crystal capacitive loading, supply voltage on the oscillator, temperature, and aging. the jitter in the low-speed data rate mu st be less than 10ns. 1.5 k ? d+ d? v reg (3.3v) usb low-speed cable mcu universal serial bus module (usb) hardware description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 175 11.7 hardware description the usb module as prev iously shown in figure 11-2 contains three functional blocks: the lo w-speed usb transceiver, the usb control logic, and the usb registers. the following details the f unction of the regulator, transceiver, and cont rol logic. see 11.8 i/o registers for details of register settings. 11.7.1 voltage regulator the usb data lines are required by the usb specific ation to have an output voltage between 2.8v and 3.6v. the data lin es also are required to have an external 1.5k ? pull-up resistor connec ted between a data line and a voltage source between 3.0v and 3.6v. figure 11-10 shows the worst case electrical connecti on for the vo ltage regulator. figure 11-10. regulator electrical connections 11.7.2 usb transceiver the usb transceiver provides the physi cal interface to the usb d+ and d? data lines. the transceiver is composed of two parts: an output drive circuit and a receiver. r1 d+ d? usb cable low-speed transceiver r2 r2 host or hub 3.3v regulator 4.0v to 5.5v usb data lines r1 = 1.5k ? 5% r2 = 15k ? 5% universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 176 universal serial bus module (usb) freescale semiconductor 11.7.2.1 output driver characteristics the usb transceiver uses a differentia l output driver to drive the usb data signal onto the usb c able. the static output sw ing of the driver in its low state is below the v ol of 0.3v with a 1.5k ? load to 3.6v and in its high state is above the v oh of 2.8v with a 15k ? load to ground. the output swings between th e differential high an d low state are well balanced to minimize signal skew. slew rate control on the driver is used to minimize the radi ated noise and cross talk . the driver?s outputs support 3-state operation to achieve bidirectional ha lf duplex operation. the driver can tolerate a voltage on t he signal pins of ?1 .0v to 5.5v with respect to local ground reference without damage. 11.7.2.2 low speed (1.5 m bps) driver characteristics the rise and fall time of the signals on this cable are gr eater than 75ns and less than 300ns. the ed ges are matched to within 20% to minimize rfi emissions and signal skew. usb data transmission is done with di fferential signals. a differential input receiver is used to accept the usb data signal. a differential 1 on the bus is represented by d+ being at least 200mv more positive than d? as seen at the receiver, and a differential 0 is represented by d? being at least 200mv more positive t han d+ as seen at the receiver. the signal cross over point must be between 1.3v and 2.0v. figure 11-11. recei ver characteristics one bit time (1.5 mb/s) signal pins pass output spec levels with minimal reflections and ringing v se (min.) v se (max) v ss universal serial bus module (usb) hardware description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 177 the receiver features an input sensitivity of 200mv when both differential data inputs are in the differential comm on mode range of 0.8v to 2.5v as shown in figure 11-12 . in addition to the differential receiver, there is a singl e-ended receiver (sch mitt trigger) fo r each of the two data lines. figure 11-12. differenti al input sensitivity range 11.7.2.3 receiver data jitter the data receivers for all types of devices must be able to properly decode the differential data in the pres ence of jitter. the more of the bit time that any data edge can occupy and still be decoded, the more reliable the data transfer will be. data receivers are required to decode differential data transiti ons that occur in a window plus and minus a nominal quarter bit time from the nominal (center ed) data edge position. jitter will be caused by the delay mi smatches and by mismatches in the source and destination data rates (frequencies). the receive data jitter budget for low speed is given in section 20. electri cal specifications . the specification include s the consecutive (nex t) and paired transition values for each source of jitter. 11.7.2.4 data source jitter the source of data can have some variat ion (jitter) in t he timing of edges of the data transmitted. the time between any set of data transitions is n t period jitter time, where n is the number of bits between the transitions and t period is defined as the actual period of the data rate. the data jitter is measured with th e same capacitive load used for maximum rise and fall time s and is measured at t he crossover points of the data lines as shown in figure 11-13 . differential output crossover voltage range differential input voltage range input voltage range (volts) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 ?1.0 5.5 universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 178 universal serial bus module (usb) freescale semiconductor figure 11-13. data jitter for low-speed transmissions, the ji tter time for any consecutive differential data transiti ons must be within 25ns and within 10ns for any set of paired diff erential data transitions. these jitter numbers include timing variati ons due to differential buff er delay, rise/fall time mismatches, internal clock source ji tter, noise and ot her random effects. 11.7.2.5 data signal rise and fall time the output rise time and fall time are measured between 10% and 90% of the signal. edge transit ion time for the rising and falling edges of low- speed signals is 75ns (minim um) into a capacitive load (c l ) of 200pf and 300ns (maximum) into a capacit ive load of 600pf. the rising and falling edges should be trans itioning (monotonic) sm oothly when driving the cable to avoid excessive emi. figure 11-14. data si gnal rise and fall time consecutive transitions t period differential data lines crossover points paired transitions jitter t r differential data lines t f rise time fall time 10% 90% 90% 10% low speed: 75ns at c l = 200pf, 300ns at c l = 600 pf c l c l + + universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 179 11.7.3 usb control logic the usb control logic m anages data movement between the cpu and the transceiver. the control logic handles both transmit and receive operations on the usb. it contains the logic used to manipulate the transceiver and the endpoint registers. the byte count buffer is loaded with the active transmit endpoints byte count value during trans mit operations. this same buffer is used for receive transactions to count th e number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. when transmitting, the control logic handles parallel-to-serial conversion, crc generation, nrzi encoding, and bit stuffing. when receiving, the control logi c handles sync detection, packet identification, end-of-pa cket detection, bi t (un)stuffing, nrzi decoding, crc validation, and serial -to-parallel conversion. errors detected by the control logic include bad crc, timeou t while waiting for eop, and bit stuffing violations. 11.8 i/o registers these i/o registers control and monitor usb operation: usb address r egister (uaddr) usb control regi sters 0?4 (ucr0?ucr4) usb status registers 0?1 (usr0?usr1) usb interrupt regi sters 0?2 (uir0?uir2) usb endpoint 0 data regi sters 0?7 (ue0d0?ue0d7) usb endpoint 1 data regi sters 0?7 (ue1d0?ue1d7) usb endpoint 2 data regi sters 0?7 (ue2d0?ue2d7) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 180 universal serial bus module (usb) freescale semiconductor 11.8.1 usb address register usben ? usb module enable this read/write bit enables and dis ables the usb mo dule and the usb pins. when usben is set, the usb module is enabled and the pte4 interrupt is disabled. when usben is clear, t he usb module will not respond to any tokens, usb reset and usb related interrupts are disabled, and pins pte4/d? and pte3/d+ function as high current open-drain i/o port pins pte4 and pte3. 1 = usb function enabled and pte4 interrupt is disabled 0 = usb function disabled includ ing usb interrupt, reset and reset interrupt uadd[6:0] ? usb function address these bits specify the usb address of the device. reset clears these bits. address: $0038 bit 7654321bit 0 read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset: 0*0000000 * usben bit is reset by por or lvi reset only. figure 11-15. usb addr ess register (uaddr) universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 181 11.8.2 usb interrupt register 0 eopie ? end-of-packet de tect interrupt enable this read/write bit enabl es the usb to gener ate cpu interrupt requests when the eopf bit become s set. reset clears the eopie bit. 1 = end-of-packet sequence detection can generate a cpu interrupt request 0 = end-of-packet sequence detection cannot generate a cpu interrupt request suspnd ? usb suspend bit to save power, this read/write bit should be set by the software if a 3ms constant idle stat e is detected on the us b bus. setting this bit puts the transceiver into a po wer-saving mode. the resumf flag must be cleared before se tting suspnd. software must clear this bit after the resume flag (resumf) is set while this resume interrupt flag is serviced. txd2ie ? endpoint 2 tr ansmit interrupt enable this read/write bit enabl es the transmit endpoi nt 2 to generate cpu interrupt requests when the txd2f bi t becomes set. reset clears the txd2ie bit. 1 = transmit endpoint 2 can gener ate a cpu interrupt request 0 = transmit endpoint 2 cannot generate a cp u interrupt request address: $0039 bit 7654321bit 0 read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 = unimplemented figure 11-16. usb interrupt register 0 (uir0) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 182 universal serial bus module (usb) freescale semiconductor rxd2ie ? endpoint 2 re ceive interrupt enable this read/write bit enabl es the receive endpoint 2 to gen erate cpu interrupt requests when the rxd2f bi t becomes set. reset clears the rxd2ie bit. 1 = receive endpoint 2 can gener ate a cpu interrupt request 0 = receive endpoint 2 cannot ge nerate a cpu interrupt request txd1ie ? endpoint 1 tr ansmit interrupt enable this read/write bit enabl es the transmit endpoi nt 1 to generate cpu interrupt requests when the txd1f bi t becomes set. reset clears the txd1ie bit. 1 = transmit endpoints 1 can gener ate a cpu inte rrupt request 0 = transmit endpoints 1 cannot gen erate a cpu interrupt request txd0ie ? endpoint 0 tr ansmit interrupt enable this read/write bit enabl es the transmit endpoi nt 0 to generate cpu interrupt requests when the txd0f bi t becomes set. reset clears the txd0ie bit. 1 = transmit endpoint 0 can gener ate a cpu interrupt request 0 = transmit endpoint 0 cannot generate a cp u interrupt request rxd0ie ? endpoint 0 re ceive interrupt enable this read/write bit enabl es the receive endpoint 0 to gen erate cpu interrupt requests when the rxd0f bi t becomes set. reset clears the rxd0ie bit. 1 = receive endpoint 0 can gener ate a cpu interrupt request 0 = receive endpoint 0 cannot ge nerate a cpu interrupt request universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 183 11.8.3 usb interrupt register 1 eopf ? end-of-packet detect flag this read-only bit is set when a va lid end-of-packe t sequence is detected on the d+ and d? lines. software must clear this flag by writing a logic 1 to the eopfr bit. reset clears this bit. writi ng to eopf has no effect. 1 = end-of-packet sequen ce has been detected 0 = end-of-packet sequence has not been detected rstf ? usb reset flag this read-only bit is set when a valid reset signal state is detected on the d+ and d? lines. if the urstd bit of the configuration register (config) is clear, this reset detec tion will generate an internal reset signal to reset the cpu and other periphera ls including the usb module. if the urstd bit is set, th is reset detection will generate an usb interrupt. this bit is cleared by writing a logic 1 to the rstfr bit. this bit also is cleared by a por reset. note: the usb bit in the srsr (see 8.8.2 sim reset status register (srsr) ) is also a usb reset indicator. txd2f ? endpoint 2 data transmit flag this read-only bit is set after the data stored in endpoint 2 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by wr iting a logic 1 to the txd2fr bit. address: $003a bit 7654321bit 0 read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 = unimplemented figure 11-17. usb interrupt register 1 (uir1) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 184 universal serial bus module (usb) freescale semiconductor to enable the next data packet transmissi on, tx2e also must be set. if the txd2f bit is not cleared, a nak handshak e will be returned in the next in transaction. reset clears this bit. writi ng to txd2f has no effect. 1 = transmit on endpoint 2 has occurred 0 = transmit on endpoint 2 has not occurred rxd2f ? endpoint 2 data receive flag this read-only bit is set after t he usb module has received a data packet and responded with an a ck handshake packet. software must clear this flag by writing a logic 1 to the rxd2fr bit after all of the received data has been read. software also mu st set the rx2e bit to 1 to enable the next data packet rec eption. if the rx d2f bit is not cleared, a nak handshake will be returned in the next out transaction. reset clears this bit. writi ng to rxd2f has no effect. 1 = receive on endpoint 2 has occurred 0 = receive on endpoint 2 has not occurred txd1f ? endpoint 1 data transmit flag this read-only bit is set after the dat a stored in the e ndpoint 1 transmit buffer has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writ ing a logic 1 to t he txd1fr bit. to enable the next data packet transmissi on, tx1e also must be set. if the txd1f bit is not cl eared, a nak handshake wi ll be returned in the next in transaction. reset clears this bit. writi ng to txd1f has no effect. 1 = transmit on endpoi nt 1has occurred 0 = transmit on endpoint 1has not occurred resumf ? resume flag this read-only bit is set when usb bu s activity is detected while the suspnd bit is set. software must clear this flag by wr iting a logic 1 to the resumfr bit. reset clears this bit. writing a lo gic 0 to resumf has no effect. 1 = usb bus activity has been detected 0 = no usb bus activity has been detected universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 185 txd0f ? endpoint 0 data transmit flag this read-only bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writ ing a logic 1 to t he txd0fr bit. to enable the next data packet transmissi on, tx0e also must be set. if the txd0f bit is not cl eared, a nak handshake wi ll be returned in the next in transaction. reset clears this bit. writi ng to txd0f has no effect. 1 = transmit on endpoint 0 has occurred 0 = transmit on endpoint 0 has not occurred rxd0f ? endpoint 0 data receive flag this read-only bit is set after t he usb module has received a data packet and responded with an a ck handshake packet. software must clear this flag by writing a logic 1 to the rxd0fr bit after all of the received data has been read. software also mu st set the rx0e bit to 1 to enable the next data packet rec eption. if the rx d0f bit is not cleared, the usb will respon d with a nak handshake to any endpoint 0 out tokens; but does not respond to a setup token. reset clears this bit. writi ng to rxd0f has no effect. 1 = receive on endpoint 0 has occurred 0 = receive on endpoint 0 has not occurred universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 186 universal serial bus module (usb) freescale semiconductor 11.8.4 usb interrupt register 2 eopfr ? end-of-p acket flag reset writing a logic 1 to this write-only bit w ill clear the eopf bit if it is set. writing a logic 0 to the eopfr ha s no effect. reset clears this bit. rstfr ? clear reset indicator bit writing a logic 1 to this write-only bit will clear t he rstf bit if it is set. writing a logic 0 to the rstfr has no effect. reset clears this bit. txd2fr ? endpoint 2 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txd2f bit if it is set. writing a logic 0 to t xd2fr has no effect. reset clears this bit. rxd2fr ? endpoint 2 receive flag reset writing a logic 1 to this write-only bit will clear the rxd2f bit if it is set. writing a logic 0 to rxd2fr has no effect. reset clears this bit. txd1fr ? endpoint 1 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txd1f bit if it is set. writing a logic 0 to t xd1fr has no effect. reset clears this bit. resumfr ? resume flag reset writing a logic 1 to this write-only bit will clear the resumf bit if it is set. writing to resumfr has no effect. reset clears this bit. txd0fr ? endpoint 0 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txd0f bit if it is set. writing a logic 0 to t xd0fr has no effect. reset clears this bit. rxd0fr ? endpoint 0 receive flag reset writing a logic 1 to this write-only bit will clear the rxd0f bit if it is set. writing a logic 0 to rxd0fr has no effect. reset clears this bit. address: $0018 bit 7654321bit 0 read: 00 0 0 0 0 0 0 write: eopfr rstfr txd2fr rxd2fr txd1fr resumfr txd0fr rxd0fr reset:00000000 figure 11-18. usb interrupt register 2 (uir2) universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 187 11.8.5 usb control register 0 t0seq ? endpoint 0 tr ansmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed at endpoint 0. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active fo r next endpoint 0 transmit 0 = data0 token active fo r next endpoint 0 transmit tx0e ? endpoint 0 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to e ndpoint 0. software should set this bit when data is ready to be transmi tted. it must be cleared by software when no more endpoint 0 data needs to be transmitted. if this bit is 0 or the txd0f is set, the usb will re spond with a nak handshake to any endpoint 0 in tokens. reset cl ears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rx0e ? endpoint 0 receive enable this read/write bit enabl es a receive to occur when the usb host controller sends an out token to endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxd0f is set, the usb wil l respond with a nak handshake to any endpoint 0 out to kens; but does not respond to a setup token. rese t clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak address: $003b bit 7654321bit 0 read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 figure 11-19. usb contro l register 0 (ucr0) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 188 universal serial bus module (usb) freescale semiconductor tp0siz3?tp0siz0 ? endpoint 0 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for endpoint 0. these bits are cleared by reset. 11.8.6 usb control register 1 t1seq ? endpoint 1 tr ansmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed to endpoint 1. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active fo r next endpoint 1 transmit 0 = data0 token active fo r next endpoint 1 transmit stall1 ? endpoint 1 force stall bit this read/write bit caus es endpoint 1 to retu rn a stall handshake when polled by either an in or ou t token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default tx1e ? endpoint 1 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to endpoint 1. the appropriate endpoint enable bit, enable1 bit in the ucr3 register , also should be set. software should set the tx1e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. address: $003c bit 7654321bit 0 read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 figure 11-20. usb contro l register 1 (ucr1) universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 189 if this bit is 0 or the txd1f is set, the usb will re spond with a nak handshake to any endpoint 1 directed in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak fresum ? force resume this read/write bit forces a resume st ate (k or non-idle state) onto the usb data lines to init iate a remote wakeup. software should control the timing of the forc ed resume to be between 10 and 15 ms. setting this bit will not cause the resumf bit to be set. 1 = force data lines to k state 0 = default tp1siz3?tp1siz0 ? endpoint 1 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for endpoint 1. these bits are cleared by reset. 11.8.7 usb control register 2 t2seq ? endpoint 2 tr ansmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed to endpoint 2. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active fo r next endpoint 2 transmit 0 = data0 token active fo r next endpoint 2 transmit address: $0019 bit 7654321bit 0 read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 figure 11-21. usb contro l register 2 (ucr2) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 190 universal serial bus module (usb) freescale semiconductor stall2 ? endpoint 2 force stall bit this read/write bit caus es endpoint 2 to retu rn a stall handshake when polled by either an in or ou t token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default tx2e ? endpoint 2 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to endpoint 2. the appropriate endpoint enable bit, enable2 bit in the ucr3 register , also should be set. software should set the tx2e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. if this bit is 0 or the txd2f is set, the usb will re spond with a nak handshake to any endpoint 2 directed in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rx2e ? endpoint 2 receive enable this read/write bit enabl es a receive to occur when the usb host controller sends an out token to endpoint 2. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxd2f is set, the usb wil l respond with a nak handshake to any endpoint 2 out tokens. reset clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak tp2siz3?tp2siz0 ? endpoint 2 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for endpoint 2. these bits are cleared by reset. universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 191 11.8.8 usb control register 3 tx1st ? endpoint 0 transmit first flag this read-only bit is set if the endpoint 0 data transmit flag (txd0f) is set when the usb control logic is setting the endpoint 0 data receive flag (rxd0f). in other words, if an unserviced endpoint 0 transmit flag is still set at the end of an endpoint 0 recepti on, then this bi t will be set. this bit lets the firmware know that th e endpoint 0 transmission happened before the endpoi nt 0 reception. reset clears this bit. 1 = in transaction occu rred before setup/out 0 = in transaction occu rred after setup/out tx1str ? clear endpoint 0 transmit first flag writing a logic 1 to this write-only bit will cl ear the tx1st bit if it is set. writing a logic 0 to t he tx1str has no effect. reset clears this bit. ostall0 ? endpoint 0 force stall bit for out token this read/write bit caus es endpoint 0 to retu rn a stall handshake when polled by an out token by the usb host controller. the usb hardware clears this bit when a set up token is received. reset clears this bit. 1 = send stall handshake 0 = default address: $001a bit 7654321bit 0 read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 = unimplemented * pullen bit is reset by por or lvi reset only. figure 11-22. usb contro l register 3 (ucr3) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 192 universal serial bus module (usb) freescale semiconductor istall0 ? endpoint 0 force stall bit for in token this read/write bit caus es endpoint 0 to retu rn a stall handshake when polled by an in token by the usb host c ontroller. the usb hardware clears this bit when a set up token is received. reset clears this bit. 1 = send stall handshake 0 = default pullen ? pull-up enable this read/write bit controls the pull-up option for the usb d? pin if the usb module is enabled. 1 = configure d? pin to have internal pull-up 0 = disconnect d? pin internal pull-up enable2 ? endpoint 2 enable this read/write bi t enables endpoint 2 and al lows the usb to respond to in or out packets addressed to endpoint 2. reset clears this bit. 1 = endpoint 2 is ena bled and can respond to an in or out token 0 = endpoint 2 is disabled enable1 ? endpoint 1 enable this read/write bi t enables endpoint 1 and al lows the usb to respond to in packets addressed to endpoi nt 1. reset clears this bit. 1 = endpoint 1 is enabled and can respond to an in token 0 = endpoint 1 is disabled universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 193 11.8.9 usb control register 4 usb control register 4 di rectly controls the usb data pins d+ and d?. if the fusbo bit, and the usben bit of the usb address register (uaddr) are set, the output buffers of t he usb modules are enabled and the corresponding levels of the usb data pins d+ and d? are equal to the values set by the fdp and the fdm bits. fusbo ? force usb output this read/write bi t enables the usb output buffers. 1 = enables usb output buffers 0 = usb module in normal operation fdp ? force d+ this read/write bit det erminates the out put level of d+. 1 = d+ at output high level 0 = d+ at output low level fdm ? force d? this read/write bit det erminates the out put level of d?. 1 = d? at output high level 0 = d? at output low level note: customers must be very careful w hen setting the ucr4 register. when the fusbo and the us ben bits are set, the usb module is in output mode and it will not re cognize any usb signals including the usb reset signal. the ucr4 register is used for some special applications. customers are not nor mally expected to use this register. address: $001b bit 7654321bit 0 read: 0 0 0 0 0 fusbo fdp fdm write: reset:00000000 = unimplemented figure 11-23. usb contro l register 4 (ucr4) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 194 universal serial bus module (usb) freescale semiconductor 11.8.10 usb status register 0 r0seq ? endpoint 0 re ceive sequence bit this read-only bit indica tes the type of data packet last received for endpoint 0 (data0 or data1). 1 = data1 token received in last endpoint 0 receive 0 = data0 token received in last endpoint 0 receive setup ? setup token detect bit this read-only bit indi cates that a valid setup token has been received. 1 = last token rece ived for endpoint 0 was a setup token 0 = last token receiv ed for endpoint 0 was not a setup token rp0siz3?rp0siz0 ? endpoint 0 receive data packet size these read-only bits store the number of data bytes received for the last out or setup tr ansaction for endpoint 0. address: $003d bit 7654321bit 0 read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset = unimplemented figure 11-24. usb status register 0 (usr0) universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 195 11.8.11 usb status register 1 r2seq ? endpoint 2 re ceive sequence bit this read-only bit indica tes the type of data packet last received for endpoint 2 (data0 or data1). 1 = data1 token received in last endpoint 2 receive 0 = data0 token received in last endpoint 2 receive txack ? ack tok en transmit bit this read-only bit indica tes that an ack token has been transmitted. this bit is updated at the end of the data transmission. 1 = last token transmitted fo r endpoint 0 wa s an ack token 0 = last token transmitted for endp oint 0 was not an ack token txnak ? nak tok en transmit bit this read-only bit indica tes that a txnak token has been transmitted. this bit is updated at the end of t he data transmission. 1 = last token transmitted fo r endpoint 0 wa s a nak token 0 = last token transmitted for endpoint 0 was not a nak token txstl ? stall token transmit bit this read-only bit indica tes that a stall token has been transmitted. this bit is updated at the end of the data transmission. 1 = last token transmitted for endpoint 0 was a stall token 0 = last token transmitted for endp oint 0 was not a stall token rp2siz3?rp2siz0 ? endpoint 2 receive data packet size these read-only bits store the number of data bytes received for the last out transaction for endpoint 2. address: $003e bit 7654321bit 0 read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u000uuuu = unimplemented u = unaffected by reset figure 11-25. usb status register 2 (usr1) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 196 universal serial bus module (usb) freescale semiconductor 11.8.12 usb endpoint 0 data registers ue0rx7?ue0rx0 ? endpoint 0 receive data buffer these read-only bits are serially loaded with out token or setup token data directed at en dpoint 0. the data is received over the usb?s d+ and d? pins. ue0tx7?ue0tx0 ? endpoint 0 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 0. address: $0020 ue0d0 bit 7654321bit 0 read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t 04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset address: $0027 ue0d7 read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t 74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset figure 11-26. usb endpoint 0 da ta registers (ue0d0?ue0d7) universal serial bus module (usb) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 197 11.8.13 usb endpoint 1 data registers ue1tx7?ue1tx0 ? endpoint 1 trans mit or receive data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 1. address: $0028 ue1d0 bit 7654321bit 0 read: write: ue1t07 ue1t06 ue1t05 ue1t 04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset address: $002f ue1d7 read: write: ue1t77 ue1t76 ue1t75 ue1t 74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset = unimplemented figure 11-27. usb endpoint 1 da ta registers (ue1d0?ue1d7) universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 198 universal serial bus module (usb) freescale semiconductor 11.8.14 usb endpoint 2 data registers ue2rx7?ue2rx0 ? endpoint 2 receive data buffer these read-only bits are serially loaded with out token data directed at endpoint 2. the data is received over the usb?s d+ and d? pins. ue2tx7?ue2tx0 ? endpoint 2 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 2. address: $0030 ue2d0 bit 7654321bit 0 read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t 04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset address: $0037 ue2d7 read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t 74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset figure 11-28. usb endpoint 2 da ta registers (ue2d0?ue2d7) universal serial bus module (usb) usb interrupts MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 199 11.9 usb interrupts the usb module is capabl e of generating interr upts and causing the cpu to execute the usb interrupt se rvice routine. ther e are three types of usb interrupts: end-of-transaction interrupts signify either a completed transaction receive or transmit transaction. resume interrupts signify that t he usb bus is reactivated after having been suspended. end-of-packet interrupts signify that a low-speed end-of-packet signal was detected. all usb interrupts shar e the same interrupt vector. firmware is responsible for determining which interrupt is active. 11.9.1 usb end-of-transaction interrupt there are five possible end- of-transaction interrupts: endpoint 0 or 2 receive endpoint 0, 1 or 2 transmit end-of-transaction in terrupts occur as detailed in the following sections. universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 200 universal serial bus module (usb) freescale semiconductor 11.9.1.1 receive control endpoint 0 for a control out transaction dire cted at endpoint 0, the usb module will generate an interrupt by setting t he rxd0f flag in the uir0 register. the conditions necessary for the inte rrupt to occur are shown in the flowchart in figure 11-29 . figure 11-29. out tok en data flow for receive endpoint 0 valid out token received for endpoint 0 error free data packet? no response from usb function set rxd0f to 1 (rxd0ie = 1) no interrupt accept data no response from usb function timeout n set/clear r0seq bit valid data token received for endpoint 0? usb module enabled? (usben = 1) endpoint 0 receive not stalled? (ostall0 = 0) endpoint 0 receive ready to receive? (rx0e = 1) and (rxd0f = 0) receive control endpoint interrupt enabled? valid transaction interrupt generated send stall handshake send nak handshake no response from usb function ignore transaction y y y y y y n n n n n y universal serial bus module (usb) usb interrupts MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 201 setup transactions cann ot be stalled by the usb function. a setup received by a control endp oint will clear the is tall0 and ostall0 bits. the conditions for receiving a setup interrupt are shown in figure 11-30 . figure 11-30. setup token data flow for receive endpoint 0 error free data packet? no response from usb function set rxd0f to 1 (rxd0ie = 1) no interrupt accept data n set/clear r0seq bit valid setup token received for endpoint 0? usb module enabled? (usben = 1) endpoint 0 receive ready to receive? (rx0e = 1) and (rxd0f = 0) receive control endpoint interrupt enabled? valid transaction interrupt generated no response from usb function no response from usb function ignore transaction y y y y y n n n set setup bit to 1 universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 202 universal serial bus module (usb) freescale semiconductor 11.9.1.2 transmit control endpoint 0 for a control in transaction directed at endpoint 0, the usb module will generate an interrupt by setting the tx d0f flag in the ui r1 register. the conditions necessary for the interrupt to occur are shown in the flowchart in figure 11-31 . figure 11-31. in token data fl ow for transmit endpoint 0 valid in token received for endpoint 0 send stall handshake set txd0f to 1 (txd0ie = 1) no interrupt send data n data pid set by t0seq usb module enabled? (usben = 1) transmit endpoint not stalled by firmware (istall0 = 0)? transmit endpoint ready to transfer? (tx0e = 1) and (txd0f = 0) transmit endpoint interrupt enabled? valid transaction interrupt generated send nak handshake y y y y y n n n n y no response from usb function ack received and no timeout condition occurs? no response from usb function universal serial bus module (usb) usb interrupts MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor univers al serial bus module (usb) 203 11.9.1.3 transmit endpoint 1 for an in transaction directed at endpoint 1, the usb module will generate an interrupt by setting the txd1f in t he uir1 register. the conditions necessary for the inte rrupt to occur are shown in figure 11-32 . figure 11-32. in token data fl ow for transmit endpoint 1 valid in token received for endpoint 1 send stall handshake set txd1f to 1 (txd1ie = 1) no interrupt send data n data pid set by t1seq usb module enabled? (usben = 1) transmit endpoint not stalled by firmware (stall1 = 1)? transmit endpoint ready to transfer? (tx1e = 1) and (txd1f = 0) and (ue1tr = 0) transmit endpoint enabled? (enable = 1) transmit endpoint interrupt enabled? valid transaction interrupt generated send nak handshake no response from usb function y y y y y y n n n n n y no response from usb function ack received and no timeout condition occurs? no response from usb function universal serial bus module (usb) technical data MC68HC908JG16 ? rev. 1.1 204 universal serial bus module (usb) freescale semiconductor 11.9.1.4 transmit endpoint 2 for an in transaction directed at endpoint 2, the usb module will generate an interrupt by setting the txd2f in the uir1 register. 11.9.1.5 receive endpoint 2 for an out transaction directed at endpoint 2, the usb module will generate an interrupt by setting the rxd2f in the uir1 register. 11.9.2 resume interrupt the usb module will generate a cpu interrupt if low-speed bus activity is detected after entering the suspend st ate. a transition of the usb data lines to the non-idle stat e (k state) while in the suspend mode will set the resumf flag in the uir1 register. ther e is no interrupt enable bit for this interrupt source and an in terrupt will be executed if the i-bit in the ccr is cleared. a resume interrupt can only occur while t he mcu is in the suspend mode. 11.9.3 end-of-packet interrupt the usb module ca n generate a usb interr upt upon detection of an end-of-packet signal for low-speed devices. upon detection of an end- of-packet signal, the usb module se ts the eopf bi t and will generate a cpu interrupt if the eopie bit in the uir0 register is set. MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 205 technical data ? MC68HC908JG16 section 12. serial communications interface module (sci) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.5.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 215 12.5.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 12.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 12.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .220 12.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 12.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 12.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 12.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .226 12.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.8.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 serial communications interface technical data MC68HC908JG16 ? rev. 1.1 206 serial communications interface module (sci) freescale semiconductor 12.8.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 12.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.9.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12.9.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 12.9.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 12.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 12.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 12.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 12.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . .242 12.2 introduction this section describes the serial communications interface (sci) module, which allows hi gh-speed asynchronous communications with peripheral devices and other mcus. note: references to dma (direct-memory access) and associated functions are only valid if t he mcu has a dma module. this mcu does not have the dma function. any dma -related register bits sh ould be left in their reset state for normal mcu operation. 12.3 features features of the sci modu le include the following: full-duplex operation standard mark/space non-re turn-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled trans mitter and receiver separate receiver and transmi tter cpu interrupt requests programmable transm itter output polarity baud rate clock sour ce is oscdclk (2 oscxclk) serial communications interface module (sci) features MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 207 two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framin g error detection hardware parity checking 1/16 bit-time noise detection serial communications interface technical data MC68HC908JG16 ? rev. 1.1 208 serial communications interface module (sci) freescale semiconductor 12.4 pin name conventions the generic names of th e sci i/o pins are: rxd (receive data) txd (transmit data) sci i/o (input/outpu t) lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output re flects the name of the shared port pin. table 12-1 shows the full names and the generic names of the sci i/o pins. the generic pin names appear in t he text of this section. 12.5 functional description figure 12-1 shows the structure of the sc i module. the sci allows full- duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus . the transmitter and receiver of the sci operate independent ly, although they us e the same baud rate generator. during normal oper ation, the cpu monitors the status of the sci, writes the data to be transmi tted, and processes received data. the baud rate clock source for the sci is the oscdc lk from the oscillator circuit, which is two times the crystal clock, oscxclk. table 12-1. pin name conventions generic pin names: rxd txd full pin names: ptc1/rxd ptc0/txd serial communications interface module (sci) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 209 figure 12-1. sci m odule block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 dmate orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control dmare ensci loops ensci internal bus txinv loops 3 16 pre- scaler baud divider rxd txd oscdclk serial communications interface technical data MC68HC908JG16 ? rev. 1.1 210 serial communications interface module (sci) freescale semiconductor addr.register name bit 7654321bit 0 $005a sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $005b sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $005c sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 $005d sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $005e sci status register 2 (scs2) read: bkf rpf write: reset:00000000 $005f sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0060 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:0000 000 = unimplemented r = reserved u = unaffected figure 12-2. sci i/o register summary serial communications interface module (sci) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 211 12.5.1 data format the sci uses the standard non-return-to-zero mark /space data format illustrated in figure 12-3 . figure 12-3. sci data formats 12.5.2 transmitter figure 12-4 shows the structure of the sci transmitter. the baud rate clock source fo r the sci is the oscdclk. bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity bit parity bit serial communications interface technical data MC68HC908JG16 ? rev. 1.1 212 serial communications interface module (sci) freescale semiconductor figure 12-4. sci transmitter dmate scte pen pty h876543210l 11-bit transmit stop start t8 dmate scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register dmate tc sctie tcie scte transmitter cpu interrupt request transmitter dma service request m ensci loops te txinv internal bus 3 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 sctie txd oscdclk serial communications interface module (sci) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 213 12.5.2.1 character length the transmitter can accommod ate either 8-bit or 9- bit data. the state of the m bit in sci control register 1 (scc1) deter mines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bi t (bit 8). 12.5.2.2 character transmission during an sci transmission, the transmit shift regist er shifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the tr ansmit shift register. to initiate an sci transmission: 1. enable the sci by writing a logi c 1 to the enable sci bit (ensci) in sci control r egister 1 (scc1). 2. enable the transmitter by writi ng a logic 1 to the transmitter enable bit (te) in sci cont rol register 2 (scc2). 3. clear the sci transmit ter empty bit by first reading sci status register 1 (scs1) and t hen writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, tran smitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic tr ansfers the scdr data into the transmit shift register. a logic 0 start bit automati cally goes into the least significant bit position of the transmit shift register. a lo gic 1 stop bit goes into the most signi ficant bit position. the sci transmitter empt y bit, scte, in scs1 becomes set when the scdr transfers a byte to the trans mit shift register. the scte bit indicates that the scdr c an accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmi tter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle cond ition, logic 1. if at an y time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port pin. serial communications interface technical data MC68HC908JG16 ? rev. 1.1 214 serial communications interface module (sci) freescale semiconductor 12.5.2.3 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logi c 1, transmitter logic continuously loads break characters in to the transmit shif t register. after software clears the sbk bit, the shif t register finishes transmitting the last break character and then tr ansmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the nex t character. the sci recognizes a break characte r when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing erro r bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci dat a register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in prog ress flag (rpf) bits 12.5.2.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in scc1. th e preamble is a synchronizing idle character that begins every transmission. if the te bit is clear ed during a transmission, th e txd pin becomes idle after completion of th e transmission in prog ress. clearing and then setting the te bit duri ng a transmission queues an id le character to be sent after the character currently being transmitted. serial communications interface module (sci) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 215 note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current c haracter shifts out to the txd pin. setting te after the stop bit appears on txd causes da ta previously wr itten to the scdr to be lost. toggle the te bit for a queued idle character when the scte bit becomes set and just be fore writing the nex t byte to the scdr. 12.5.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control r egister 1 (scc1) reverses the polarity of transmitted da ta. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 12.9.1 sci control register 1 .) 12.5.2.6 transmitter interrupts these conditions can ge nerate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can gene rate a transmitter cp u interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generat e transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are em pty and that no break or idle character has been generated. th e transmission complete interrupt enable bit, tcie , in scc2 enables the tc bit to generate transmitter cpu interrupt requests. serial communications interface technical data MC68HC908JG16 ? rev. 1.1 216 serial communications interface module (sci) freescale semiconductor 12.5.3 receiver figure 12-5 shows the structure of the sci receiver. 12.5.3.1 character length the receiver can accommodat e either 8-bit or 9-bi t data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when rece iving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 12.5.3.2 character reception during an sci re ception, the receive shift regi ster shifts characters in from the rxd pin. the sci data register ( scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status regi ster 1 (scs1) becomes se t, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bi t generates a receiver cpu interrupt request. serial communications interface module (sci) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 217 figure 12-5. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery dmare scrf or orie nf neie fe feie pe peie dmare scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request dma service request cpu interrupt request sci data register r8 dmare orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 3 16 scp1 scp0 scr2 scr1 scr0 scrie dmare oscdclk rxd serial communications interface technical data MC68HC908JG16 ? rev. 1.1 218 serial communications interface module (sci) freescale semiconductor 12.5.3.3 data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 12-6 ): after every start bit after the receiver detects a data bit change from l ogic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of t he next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asyn chronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 12-6. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd serial communications interface module (sci) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 219 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 12-2 summarizes t he results of the start bit verification samples. start bit verification is not successful if any two of the three verification samples are logic 1s. if start bit ve rification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at r t8, rt9, and rt10. table 12-3 summarizes the results of the data bit samples. table 12-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 12-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 serial communications interface technical data MC68HC908JG16 ? rev. 1.1 220 serial communications interface module (sci) freescale semiconductor note: the rt8, rt9, and rt10 samp les do not affect star t bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verifica tion, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 12-4 summarizes the resu lts of the stop bit samples. 12.5.3.4 framing errors if the data recovery l ogic does not detect a logi c 1 where the stop bit should be in an in coming character, it sets t he framing error bit, fe, in scs1. a break character also sets t he fe bit because a break character has no stop bit. the fe bit is set at the same time that t he scrf bit is set. 12.5.3.5 baud rate tolerance a transmitting device may be operat ing at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. then a noise error occurs. if more t han one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate table 12-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 serial communications interface module (sci) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 221 tolerance is much more than the degree of misalignm ent that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within characters corrects misali gnments between trans mitter bit times and receiver bit times. slow data tolerance figure 12-7 shows how much a slow received character can be misaligned without causing a noise error or a fr aming error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at r t8, rt9, and rt10. figure 12-7. slow data for an 8-bit character, data sampling of the st op bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 12-7 , the receiver counts 154 rt cycles at the point when the count of t he transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a slow 8- bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------- ------------ - 100 4.54% = serial communications interface technical data MC68HC908JG16 ? rev. 1.1 222 serial communications interface module (sci) freescale semiconductor with the misaligned character shown in figure 12-7 , the receiver counts 170 rt cycles at the point when the count of t he transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a slow 9- bit character with no errors is fast data tolerance figure 12-8 shows how much a fast received character can be misaligned without causing a noise error or a framing erro r. the fast stop bit ends at rt10 instead of rt16 but is st ill there for t he stop bit data samples at rt8, rt9, and rt10. figure 12-8. fast data for an 8-bit character, data sampling of the st op bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 12-8 , the receiver counts 154 rt cycles at the point when the count of t he transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a fast 8-bi t character with no errors is 170 163 ? 170 ------------- ------------ - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------- ------------ - 100 3.90% = serial communications interface module (sci) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 223 for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 12-8 , the receiver counts 170 rt cycles at the point when the count of t he transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a fast 9- bit character with no errors is 12.5.3.6 receiver wakeup so that the mcu can ignore tr ansmissions intended only for other receivers in multiple-receiver system s, the receiver can be put into a standby state. setting the receiver wa keup bit, rwu, in scc2 puts the receiver into a standby state during which re ceiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a rece ived character. when the wake bit is set, an address mark wakes t he receiver from the standby state by clearing the rwu bit. the addr ess mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they ar e the same, the receiv er remains awake and processes the characters that fo llow. if they are not the same, software can set the rwu bit and put the rece iver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle char acter that wakes the receiver does not set the receiver idle bit, idle , or the sci receiver 170 176 ? 170 ------------ ------------- - 100 3.53% = serial communications interface technical data MC68HC908JG16 ? rev. 1.1 224 serial communications interface module (sci) freescale semiconductor full bit, scrf. the idle line type bi t, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: with the wake bit clear , setting the rwu bit afte r the rxd pin has been idle may cause the receiver to wake up immediately. 12.5.3.7 receiver interrupts the following sources can gene rate cpu interrupt re quests from the sci receiver: sci receiver full ( scrf) ? the scrf bit in scs1 indicates that the receive shift register has tran sferred a characte r to the scdr. scrf can generate a receiver cp u interrupt request. setting the sci receive interrupt enable bit, s crie, in scc2 enables the scrf bit to generate rece iver cpu interrupts. idle input (idle) ? the idle bit in scs1 i ndicates that 10 or 11 consecutive logic 1s shifted in from the rxd pi n. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 12.5.3.8 error interrupts the following receiver error flags in scs1 can generat e cpu interrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enabl e bit, neie, in scc3 enables nf to generate sci erro r cpu interrupt requests. serial communications interface module (sci) low-power modes MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 225 framing error (fe) ? the fe bit in scs1 is se t when a logic 0 occurs where the receiver expec ts a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to gener ate sci error cpu interrupt requests. 12.6 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 12.6.1 wait mode the sci module remains active af ter the execution of a wait instruction. in wait m ode, the sci module register s are not accessible by the cpu. any enabled c pu interrupt request fr om the sci module can bring the mcu out of wait mode. if sci module functions are not requ ired during wait mode, reduce power consumption by disabling the m odule before executing the wait instruction. refer to 8.7 low-power modes for information on ex iting wait mode. 12.6.2 stop mode the sci module is inactive after the execution of a st op instruction. the stop instructio n does not affect sci r egister states. sci module operation resumes after an external interrupt. because the internal clock is inacti ve during stop m ode, entering stop mode during an sci transmission or reception results in invalid data. refer to 8.7 low-power modes for information on exiting stop mode. serial communications interface technical data MC68HC908JG16 ? rev. 1.1 226 serial communications interface module (sci) freescale semiconductor 12.7 sci during break module interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 12.8 i/o signals port c shares two of its pins with the sci module. the two sci i/o pins are: ptc0/txd ? transmit data ptc1/rxd ? receive data 12.8.1 txd (transmit data) the ptc0/txd pin is the se rial data output from the sci transmitter. the sci shares the ptc0/txd pin with port c. when the sci is enabled, the ptc0/txd pin is an output regardless of the state of the ddrc0 bit in data direction register c (ddrc). 12.8.2 rxd (receive data) the ptc1/rxd pin is the serial data input to the sci receiver. the sci shares the ptc1/rxd pin with port c. when th e sci is enabled, the ptc1/rxd pin is an input regardless of the state of the ddrc1 bit in data direction register c (ddrc). serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 227 12.9 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 12.9.1 sci control register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type serial communications interface technical data MC68HC908JG16 ? rev. 1.1 228 serial communications interface module (sci) freescale semiconductor loops ? loop mode select bit this read/write bit enabl es loop mode operatio n. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. re set clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enabl es the sci and the sc i baud rate generator. clearing ensci sets the scte and tc bits in sc i status register 1 and disables transmitter interrupt s. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter out put not inverted note: setting the txinv bit inve rts all transmitted values , including idle, break, start, and stop bits. address: $005a bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 12-9. sci cont rol register 1 (scc1) serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 229 m ? mode (character length) bit this read/write bit deter mines whether sci characters are eight or nine bits long. (see table 12-5 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit deter mines which condition wakes up the sci: a logic 1 (address mark) in the most si gnificant bit posi tion of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit deter mines when the sci star ts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but re quires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit c ount begins afte r stop bit 0 = idle character bit c ount begins after start bit pen ? parity enable bit this read/write bit ena bles the sci pari ty function. (see table 12-5 .) when enabled, the parity function in serts a parity bit in the most significant bit position. (see figure 12-3 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled serial communications interface technical data MC68HC908JG16 ? rev. 1.1 230 serial communications interface module (sci) freescale semiconductor pty ? parity bit this read/write bit determines w hether the sci generates and checks for odd parity or even parity. (see table 12-5 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. 12.9.2 sci control register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to gener ate transmitter cpu interrupt requests ? enables the tc bi t to generate transmi tter cpu interrupt requests ? enables the scrf bit to gener ate receiver cpu interrupt requests ? enables the idle bit to gene rate receiver cpu interrupt requests table 12-5. character format selection control bits character format m pen and pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 231 enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bi t enables the scte bit to generate sci transmitter cpu interrupt requests. re set clears t he sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission comple te interrupt enable bit this read/write bit enable s the tc bit to generat e sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bi t enables the scrf bit to generate sci receiver cpu interrupt requests. re set clears t he scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to gener ate sci receiver cpu interrupt requests. rese t clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabl ed to generate cp u interrupt requests address: $005b bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 12-10. sci cont rol register 2 (scc2) serial communications interface technical data MC68HC908JG16 ? rev. 1.1 232 serial communications interface module (sci) freescale semiconductor te ? transmitt er enable bit setting this read/write bit begin s the transmission by sending a preamble of 10 or 11 logi c 1s from the transmit shift register to the txd pin. if software clears the te bi t, the transmitter completes any transmission in progress before the tx d returns to the idle condition (logic 1). clearing and then setti ng te during a transmission queues an idle character to be sent af ter the character currently being transmitted. reset clears the te bit. 1 = transmitt er enabled 0 = transmitt er disabled note: writing to the te bit is not allowed when the enab le sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not a ffect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed w hen the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a st andby state during which receiver interrupt s are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clear s the rwu bit. rese t clears the rwu bit. 1 = standby state 0 = normal operation serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 233 sbk ? send break bit setting and then clearing this r ead/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break charac ters being transmitted note: do not toggle the sbk bi t immediately after se tting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. 12.9.3 sci control register 3 sci control register 3: stores the ninth sci data bit rece ived and the ninth sci data bit to be transmitted enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts parity error interrupts address: $005c bit 7654321bit 0 read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 = unimplemented u = unaffected figure 12-11. sci cont rol register 3 (scc3) serial communications interface technical data MC68HC908JG16 ? rev. 1.1 234 serial communications interface module (sci) freescale semiconductor r8 ? received bit 8 when the sci is receiving 9-bit char acters, r8 is the read-only ninth bit (bit 8) of the received characte r. r8 is received at the same time that the scdr receiv es the other 8 bits. when the sci is receiving 8-bit charac ters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmi tting 9-bit characters , t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. re set has no effect on the t8 bit. dmare ? dma receive enable bit caution: the dma module is not included on th is mcu. writing a logic 1 to dmare or dmate may adverse ly affect mcu performance. 1 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) 0 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) dmate ? dma transfer enable bit caution: the dma module is not included on th is mcu. writing a logic 1 to dmare or dmate may adverse ly affect mcu performance. 1 = scte dma service requests enabled; scte cpu interrupt requests disabled 0 = scte dma service requests disabled; scte cpu interrupt requests enabled serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 235 orie ? receiver overr un interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt r equests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the noise error bi t, ne. reset clears neie. 1 = sci error cpu interrupt r equests from ne bit enabled 0 = sci error cpu interrupt r equests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt r equests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the par ity error bit, pe. (see 12.9.4 sci status register 1 .) reset clears peie. 1 = sci error cpu interrupt r equests from pe bit enabled 0 = sci error cpu interrupt r equests from pe bit disabled serial communications interface technical data MC68HC908JG16 ? rev. 1.1 236 serial communications interface module (sci) freescale semiconductor 12.9.4 sci status register 1 sci status register 1 (s cs1) contains flags to signal these conditions: transfer of scdr data to trans mit shift register complete transmission complete transfer of receive shift r egister data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmi tter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal operation, clear the sct e bit by reading sc s1 with scte set and then writing to scdr. re set sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $005d bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 12-12. sci status register 1 (scs1) serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 237 tc ? transmission complete bit this read-only bit is set when the sc te bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preambl e or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queuei ng data, preambl e, and break and the transmission actually star ting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf c an generate an sci receiver cpu interrupt request. w hen the scrie bit in scc2 is set, scrf generates a cpu inte rrupt request. in norm al operation, clear the scrf bit by readi ng scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in s cc2 is also set. clear the idle bit by reading scs1 with idle set a nd then reading the scdr. after the receiver is enabled, it must receive a valid c haracter that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. rese t clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is se t when software fails to read the scdr before the receive shift regist er receives the next character. the or bit generates an sci error cpu interrupt request if the orie serial communications interface technical data MC68HC908JG16 ? rev. 1.1 238 serial communications interface module (sci) freescale semiconductor bit in scc3 is also set. the data in the shift regist er is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. rese t clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an over run to occur between reads of scs1 and scdr in the fl ag-clearing sequence. figure 12-13 shows the normal flag- clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear t he or bit because or was not set when scs1 was read. byte 2 caused the ov errun and is lost. the next flag- clearing sequence read s byte 3 in the scd r instead of byte 2. in applications that are subject to software la tency or in which it is important to know which byte is lost due to an ov errun, the flag- clearing routine c an check the or bit in a se cond read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an nf cpu inte rrupt request if the neie bit in scc3 is also set. clear the nf bit by reading sc s1 and then reading the scdr. reset cl ears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 239 figure 12-13. fl ag clearing sequence pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is al so set. clear the pe bit by reading scs1 with pe set and then readi ng the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 serial communications interface technical data MC68HC908JG16 ? rev. 1.1 240 serial communications interface module (sci) freescale semiconductor 12.9.5 sci status register 2 sci status register 2 co ntains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bi t in scc3 is cleared. bkf does not generate a cpu interrupt r equest. clear bkf by reading scs2 with bkf set and then readi ng the scdr. once cleared, bkf can become set again only after logic 1s again appear on the rxd pin followed by another br eak character. reset clears the bkf bit. 1 = break character detected 0 = no break ch aracter detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detec ts a logic 0 during the rt1 time period of t he start bit search. rp f does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. pol ling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $005e bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 12-14. sci status register 2 (scs2) serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 241 12.9.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and tran smit shift registers. r7/t7?r0/t0 ? receive/transmit data bits reading the sci data register a ccesses the read-only received data bits, r7:r0. writing to the sci data r egister writes the data to be transmitted, t7:t0. reset has no ef fect on the sci data register. note: do not use read/modify/write inst ructions on the sci data register. address: $005f bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 12-15. sci data register (scdr) serial communications interface technical data MC68HC908JG16 ? rev. 1.1 242 serial communications interface module (sci) freescale semiconductor 12.9.7 sci baud rate register the baud rate register (scbr) selects the baud rate for bo th the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 12-6 . reset clears scp1 and scp0. scr2?scr0 ? sci baud rate select bits these read/write bits select the sc i baud rate divisor as shown in table 12-7 . reset clears scr2?scr0. address: $0060 bit 7654321bit 0 read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:0000 000 = unimplemented r = reserved figure 12-16. sci baud rate register (scbr) table 12-6. sci baud rate prescaling scp1 and scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 serial communications interface module (sci) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 243 use this formula to calc ulate the sci baud rate: where: sci clock source = oscdclk pd = prescaler divisor bd = baud rate divisor table 12-8 shows the sci baud rates that can be generated with a 24mhz oscdclk (oscxclk=12mh z) as sci clock source. table 12-7. sci baud rate selection scr2, scr1, and scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate sci clock source 48 pd bd ---------------- -------------- -------------- - = serial communications interface technical data MC68HC908JG16 ? rev. 1.1 244 serial communications interface module (sci) freescale semiconductor table 12-8. sci baud ra te selection examples scp1 and scp0 prescaler divisor (pd) scr2, scr1, and scr0 baud rate divisor (bd) baud rate (oscdclk=24mhz) 00 1 000 1 baud rate settings not recommended 00 1 001 2 00 1 010 4 00 1 011 8 00 1 100 16 00 1 101 32 00 1 110 64 00 1 111 128 01 3 000 1 01 3 001 2 01 3 010 4 01 3 011 8 01 3 100 16 01 3 101 32 01 3 110 64 01 3 111 128 10 4 000 1 10 4 001 2 10 4 010 4 10 4 011 8 10 4 100 16 10 4 101 32 10 4 110 64 10 4 111 128 11 13 000 1 38461.54 11 13 001 2 19230.77 11 13 010 4 9615.38 11 13 011 8 4807.69 11 13 100 16 2403.85 11 13 101 32 1201.92 11 13 110 64 600.96 11 13 111 128 300.48 MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 245 technical data ? MC68HC908JG16 section 13. analog-to-digital converter (adc) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 13.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 13.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 13.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 13.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.7.1 adc analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . 250 13.7.2 adc analog ground pin (v ssa ). . . . . . . . . . . . . . . . . . . . . 250 13.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 250 13.7.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . 250 13.7.5 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 250 13.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .251 13.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 253 analog-to-digital converter (adc) technical data MC68HC908JG16 ? rev. 1.1 246 analog-to-digital converter (adc) freescale semiconductor 13.2 introduction this section describes the analog-to-digital converter (adc). the adc is a 8-channel 8-bit succe ssive approximation adc. 13.3 features features of the ad c module include: eight channels with multiplexed input linear successive approximation 8-bit resolution single or cont inuous conversion conversion complete flag or conversion complete interrupt addr.register name bit 7654321bit 0 $0061 adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $0062 adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $0063 adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 13-1. adc i/o register summary analog-to-digital converter (adc) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 247 13.4 functional description eight adc channels are avai lable for sampling external sources at pins pta7?pta0. an analog multiplexer a llows the single adc converter to select one of the eight adc channels as adc vo ltage input (adcvin). adcvin is converted by the successi ve approximation register-based counters. the adc resolu tion is eight bits. when the conversion is completed, adc puts the result in the adc data register and sets a flag or generates an interrupt. figure 13-2 shows a block diagram of the adc. figure 13-2. adc block diagram internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock adch[4:0] adc data register adiv[2:0] aien coco disable disable adc channel x read ddra write ddra reset write pta read pta ptax/kbax /adx ddrax ptax (1 of 8 channels) analog-to-digital converter (adc) technical data MC68HC908JG16 ? rev. 1.1 248 analog-to-digital converter (adc) freescale semiconductor 13.4.1 adc port i/o pins pta7?pta0 are general-purpos e i/o pins that are shared with the adc channels. the channel select bits, adch[4:0], in the adc status and control register define which adc channel/port pin will be used as the input signal. the ad c overrides the port i/o logi c by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port regist er or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a logic 0 if the co rresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. 13.4.2 voltage conversion when the input voltage to the adc equals to v refh , the adc converts the signal to $ff (fu ll scale). if the input voltage equals to v refl , the adc converts it to $00. input voltages between v refh and v refl is a straight-line linear conver sion. all other input volt ages will result in $ff if greater than v refh and $00 if less than v refl . note: input voltage should not exceed the analog supply voltages. 13.4.3 conversion time conversion starts after a write to the adscr. one conversion will take between 16 and 17 adc clo ck cycles, therefore: for example: with a 6mhz bus clo ck and divide-by-4 pr escaler, the adc clock is 1.5mhz, then one conversion will take 10.67 s to complete. note: the adc frequency must be between t adic minimum and t adic maximum to meet adc specifications. (see 20.13 adc electrical characteristics .) 16 to17 adc cycles conversion time = adc frequency number of bus cycles = conversion time bus frequency analog-to-digital converter (adc) interrupts MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 249 13.4.4 continuous conversion in the continuous conv ersion mode, the adc cont inuously converts the selected channel filling t he adc data register wi th new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not . conversions will continue until the adco bit is clear ed. the conversion complete bit, coco, in the adc status and control register is set after each conversion and can be cleared by writing to the adc status and control regi ster or reading of the adc data register. 13.4.5 accuracy and precision the conversion process is monot onic and has no missing codes. 13.5 interrupts when the aien bit is se t, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. the interr upt vector is defined in table 2-1 . v ector addresses . 13.6 low-power modes the wait and stop inst ructions can put th e mcu in low-power consumption standby modes. 13.6.1 wait mode the adc continues norma l operation during wait mode. any enabled cpu interrupt request fro m the adc can bring t he mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by se tting the adch[4:0] bits in the adc status and control register to l ogic 1?s before executi ng the wait instruction. analog-to-digital converter (adc) technical data MC68HC908JG16 ? rev. 1.1 250 analog-to-digital converter (adc) freescale semiconductor 13.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conver sions resume when the mcu exits stop mode. allow one conver sion cycle to stabilize the analog circuitry before attempting a new adc conversion af ter exiting stop mode. 13.7 i/o signals the adc module has ei ght channels that are shar ed with port a i/o pins, pta7/kba7 /ad7?pta0/kba0 /ad0. 13.7.1 adc analog power pin (v dda ) the adc analog portion uses v dda as its power pi n. connect the v dda pin to the same vo ltage potential as v dd . external filtering may be necessary to ensure clean v dda for good results. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 13.7.2 adc analog ground pin (v ssa ) the adc analog portion uses v ssa as its ground pin. connect the v ssa pin to the same vo ltage potential as v ss . 13.7.3 adc voltage reference high pin (v refh ) v refh is the high voltage re ference for the adc. 13.7.4 adc voltage reference low pin (v refl ) v refl is the low voltage reference for the adc. 13.7.5 adc voltage in (adcvin) adcvin is the input volt age signal from one of the eight adc channels to the adc module. analog-to-digital converter (adc) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 251 13.8 i/o registers three i/o registers control and monitor adc operation: adc status and cont rol register (adscr) adc data register (adr) adc input clock register (adiclk) 13.8.1 adc status and control register function of the adc stat us and control register is described here. coco ? conversions complete bit when the aien bit is a l ogic 0, the coco is a read-only bit which is set each time a conversion is comple ted. this bit is cleared whenever the adc status and contro l register is written, or whenever the adc data register is read. reset clears this bit. if the aien bit is a logic 1, the coco becomes a read/write bit, which should be cleared to l ogic 0 for cpu to service the adc interrupt request. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not co mpleted (aien = 0) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cl eared when the dat a register is read or the status and c ontrol register is writ ten. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $0061 bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 13-3. adc status and contro l register (adscr) analog-to-digital converter (adc) technical data MC68HC908JG16 ? rev. 1.1 252 analog-to-digital converter (adc) freescale semiconductor adco ? adc continuous conversion bit when set, the adc will convert sa mples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the adc channels or reference voltages. th e five channel select bits are detailed in the table 13-1 . note: care should be taken when using a port pin as both an analog and a digital input simultaneous ly to prevent switchin g noise from corrupting the analog signal. note: recovery from the disabled stat e requires one conversion cycle to stabilize. table 13-1. mux channel select adch4 adch3 adch2 ad ch1 adch0 adc channel input select 00000 adc0 pta0/kba0/ad0 00001 adc1 pta1/kba1/ad1 00010 adc2 pta2/kba2/ad2 00011 adc3 pta3/kba3/ad3 00100 adc4 pta4/kba4/ad4 00101 adc5 pta5/kba5/ad5 00110 adc6 pta6/kba6/ad6 00111 adc7 pta7/kba7/ad7 01000 unused (1) ? 11100 11101 ? v refh 11 1 1 0 ? v refhl 11 1 1 1 adc power off notes : 1. if any unused channels are selected, th e resulting adc conversion will be unknown. analog-to-digital converter (adc) i/o registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 253 13.8.2 adc data register one 8-bit result regist er, adc data register (a dr), is provided. this register is updated each time an adc conversion completes. 13.8.3 adc input clock register the adc input clock register (adiclk) select s the clock frequency for the adc. adiv[2:0] ? adc clock prescaler bits adiv[2:0] form a 3-bit field which selects the divide r used by the adc to generate the inte rnal adc clock. table 13-2 shows the available clock configurations. the adc clock should be set to approximately 1.5mhz. note: the adc frequency must be between t adic minimum and t adic maximum to meet adc specifications. (see 20.13 adc electrical characteristics .) address: $0062 bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 13-4. adc data register (adr) address: $0063 bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 13-5. adc input cl ock register (adiclk) analog-to-digital converter (adc) technical data MC68HC908JG16 ? rev. 1.1 254 analog-to-digital converter (adc) freescale semiconductor table 13-2. adc clock divider adiv2 adiv1 adiv0 adc clock rate 000 bus clock 1 001 bus clock 2 010 bus clock 4 011 bus clock 8 1 x x bus clock 16 x = don?t care MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 255 technical data ? MC68HC908JG16 section 14. input/output (i/o) ports 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 14.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.5.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . 264 14.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 267 14.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 271 14.8 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 14.8.1 port option control register . . . . . . . . . . . . . . . . . . . . . . .273 14.2 introduction twenty (20) bidirectional input-output (i/o) pins form fi ve parallel ports. all i/o pins are programm able as inputs or outputs. input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 256 input/output (i/o) ports freescale semiconductor note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o ports do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: 0000000 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 000000 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 0 0 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:0*0000000 * ddra7 bit is reset by por or lvi reset only. $0005 data direction register b (ddrb) read: 0000000 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: 000000 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: 0 0 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset = unimplemented figure 14-1. i/o port register summary input/output (i/o) ports introduction MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 257 $0009 data direction register e (ddre) read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $001d port option control register (pocr) read: pte20p ptdldd ptdildd pte4p pte3p pcp pbp pap write: reset:00000000 table 14-1. port contro l register bits summary port bit ddr module control pin module register control bit a 0 ddra0 adc kbi adscr (1) $0061 kbier $0017 adch[4:0] kbie[7:0] pta0/kba0/ad0 1 ddra1 pta1/kba1/ad1 2 ddra2 pta2/kba2/ad2 3 ddra3 pta3/kba3/ad3 4 ddra4 pta4/kba4/ad4 5 ddra5 pta5/kba5/ad5 6 ddra6 pta6/kba6/ad6 7 ddra7 pta7/kba7/ad7 b 0 ddrb0 ? ? ? ptb0 c 0 ddrc0 sci scc1 $005a ensci ptc0/txd 1 ddrc1 ptc1/rxd d 0?3 ddrd[0:3] ? ? ? ptd0?ptd3 e 0 ddre0 tim1 or tim2 t1sc $000a or t2sc $0040 ps[2:0] pte0/tclk 1 ddre1 tim1 t1sc0 $0010 or t1sc1 $0013 els0b:els0a or els1b:els1a pte1/t1ch01 2 ddre2 tim2 t2sc0 $0046 or t2sc1 $0049 els0b:els0a or els1b:els1a pte2/t2ch01 3 ddre3 usb uaddr $0038 usben pte3/d+ 4 ddre4 pte4/d? notes : 1. register has the highest priority control on port pin. addr.register name bit 7654321bit 0 = unimplemented figure 14-1. i/o port register summary input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 258 input/output (i/o) ports freescale semiconductor 14.3 port a port a is an 8-bit gener al-purpose bidirectional i/o port with software configurable pullups, and s hares its pins with th e keyboard interrupt module (kbi) and analog-to-digit al converter module (adc). 14.3.1 port a data register the port a data regist er contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. the port a pullup control bi t, pap, in the port opt ion control register (pocr) enables pullups on port a pins if t he respective pin is configured as an input. (see 14.8 port options .) kba7 ?kba0 ? keyboard interrupts the keyboard interrupt enable bits , kbie7?kbie0, in the keyboard interrupt enable register (kbier), enable the port a pins as external interrupt pins. (see section 16. keyboard in terrupt module (kbi) .) address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: kba7 kba6 kba5 kba4 kba3 kba2 kba1 kba0 alternative function: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 additional function: optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup figure 14-2. port a data register (pta) input/output (i/o) ports port a MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 259 ad7?ad0 ? analog-to- digital input pins ad7?ad0 are pins used fo r the input channels to the analog-to-digital converter module. the channel sele ct bits, adch[4:0], in the adc status and control register (adscr) define which port a pin will be used as an adc input and overrides an y control from the port i/o or keyboard interrupt logic. (see section 13. analog-to-digital converter (adc) .) 14.3.2 data direction register a data direction register a determine s whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables t he output buffer for the corresponding port a pin; a logi c 0 disables the output buffer. ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 14-4 shows the port a i/o logic. address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 * 0000000 * ddra7 bit is reset by por or lvi reset only. figure 14-3. data direct ion register a (ddra) input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 260 input/output (i/o) ports freescale semiconductor figure 14-4. port a i/o circuit when bit ddrax is a l ogic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-2 summarizes the operation of the port a pins. table 14-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus input/output (i/o) ports port b MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 261 14.4 port b port b is an 1-bit gener al-purpose bidirectional i/o port with software configurable pullup. 14.4.1 port b data register the port b data register contai ns the data latch for ptb0. ptb0 ? ptb0 data bit this read/write bit is so ftware programmable. da ta directio n of ptb0 pin is under control of the ddrb0 bi t in the data direction register b. reset has no effect on port b data. the port b pullup control bi t, pbp, in the port opt ion control register (pocr) enables the pul lup on ptb0 pin if configured as an input. (see 14.8 port options .) 14.4.2 data direction register b data direction register b determines whether ptb0 is an input or an output. writing a logic 1 to ddrb0 bi t enables the output buffer for the ptb0 pin; a logic 0 dis ables the output buffer. address: $0001 bit 7654321bit 0 read: 0000000 ptb0 write: reset: unaffected by reset figure 14-5. port b data register (ptb) address: $0005 bit 7654321bit 0 read: 0000000 ddrb0 write: reset:00000000 figure 14-6. data direct ion register b (ddrb) input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 262 input/output (i/o) ports freescale semiconductor ddrb0 ? data direct ion register b bit this read/write bit control ptb0 data direct ion. reset clears ddrb0, configuring ptb0 pin as input. 1 = ptb0 pin configured as output 0 = ptb0 pin configured as input note: avoid glitches on ptb0 pi n by writing to the por t b data register before changing data direction regist er b bit fr om 0 to 1. figure 14-7 shows the port b i/o circuit logic. figure 14-7. port b i/o circuit when bit ddrb0 is a logic 1, re ading address $0001 reads the ptb0 data latch. when bit dd rb0 is a logic 0, r eading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-3 summarizes the operation of the ptb0 pin. table 14-3. port b pin functions ddrb0 bit ptb0 bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrb0 pin ptb0 (3) 3. writing affects data register, but does not affect input. 1 x output ddrb0 ptb0 ptb0 read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptb0 ddrb0 ptb0 internal data bus input/output (i/o) ports port c MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 263 14.5 port c port c is a 2-bit special f unction port that shares its pins with the serial communications interface (sci) m odule. these pins have software configurable pullups. 14.5.1 port c data register the port c data register contains a data latch for each of the two port c pins. ptc[1:0] ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. the port c pullup enable bit, pcp, in the port option control register (pocr) enables pullups on ptc[1:0] if the respective pin is configured as an input. (see 14.8 port options .) txd, rxd ? sci data i/o pins the txd and rxd pins are the transmi t data output and receive data input for the sci modul e. the sci enable bit, ensci, in the sci control register 1 enables the ptc0 /txd and ptc1/rxd pins as sci txd and rxd pins and overrides any control from the port i/o. see section 12. serial communicat ions interface module (sci) . address: $0002 bit 7654321bit 0 read: 000000 ptc1 ptc0 write: reset: unaffected by reset alternative function: rxd txd additional function: optional pullup optional pullup figure 14-8. port c data register (ptc) input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 264 input/output (i/o) ports freescale semiconductor 14.5.2 data direction register c data direction register c determines whether eac h port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logi c 0 disables the output buffer. ddrc[1:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[1:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. figure 14-10 shows the port c i/o logic. figure 14-10. port c i/o circuit address: $0006 bit 7654321bit 0 read: 000000 ddrc1 ddrc0 write: reset:00000000 figure 14-9. data direct ion register c (ddrc) read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus input/output (i/o) ports port c MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 265 when bit ddrcx is a l ogic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-4 summarizes the operation of the port c pins. table 14-4. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrc[1:0] pin ptc[1:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[1:0] ptc[1:0] ptc[1:0] input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 266 input/output (i/o) ports freescale semiconductor 14.6 port d port d is an 4-bit general-purpose bidi rectional i/o port. these pins are open-drain when conf igured as output. 14.6.1 port d data register the port d data regist er contains a data latch for each of the four port d pins. note: bits 5?4 of ptd are not available in the 32-pin low-profile quad flat pack. ptd[5:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under control of the corresponding bit in data direction register d. reset has no effect on port d data. the led direct drive bit, ptdldd, in the port opt ion control register (pocr) controls the drive options for ptd5?ptd2 pins. the infrared led drive bit, ptdildd, in the pocr controls the drive options for ptd1?ptd0 pins. (see 14.8 port options .) address: $0003 bit 7654321bit 0 read: 0 0 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset additional function: 10ma sink 10ma sink 10ma sink 10ma sink 25ma sink 25ma sink figure 14-11. port d da ta register (ptd) input/output (i/o) ports port d MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 267 14.6.2 data direction register d data direction register d determines whether eac h port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logi c 0 disables the output buffer. ddrd[5:0] ? data dire ction register d bits these read/write bits control port d data direction. reset clears ddrd[5:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input port d pins are open-drain when configured as output. note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction regist er d bits fr om 0 to 1. note: for those devices packaged in a 32-pin low-profil e quad flat pack, ptd5?4 are not connected. ddrd5?4 s hould be set to a 1 to configure ptd5?4 as outputs. figure 14-13 shows the port d i/o circuit logic. address: $0007 bit 7654321bit 0 read: 0 0 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 14-12. data direct ion register d (ddrd) input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 268 input/output (i/o) ports freescale semiconductor figure 14-13. port d i/o circuit when bit ddrdx is a l ogic 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-5 summarizes the operation of the port d pins. table 14-5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[5:0] pin ptd[5:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrd[5:0] ptd[5:0] ptd[5:0] read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus input/output (i/o) ports port e MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 269 14.7 port e port e is a 5-bit special function port th at shares three of its pins with the timer interface modules (t ims) and two of its pins with the usb data pins d+ and d?. pte4 and pte3 are open-d rain when configured as output. 14.7.1 port e data register the port e data regist er contains a data latch for each of the five port e pins. pte[4:0] ? port e data bits pte[4:0] are read/write, software- programmable bits. data direction of each port e pin is under the control of the co rresponding bit in data direction register e. the pte4 and pte3 pullup enable bi ts, pte4p and pte3p, in the port option control regi ster (pocr) enable 5k ? pullups on pte4 and pte3 if the respective pin is configured as an i nput and the usb module is disabled. (see 14.8 port options .) address: $0008 bit 7654321bit 0 read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative function: d? d+ t2ch01 t1ch01 tclk additional function: optional pullup optional pullup optional pullup optional pullup optional pullup additional function: external interrupt open-drain open-drain = unimplemented figure 14-14. port e da ta register (pte) input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 270 input/output (i/o) ports freescale semiconductor the pte[2:0] pullup enable bit, pt e20p, in the port option control register (pocr) enables pullups on pte2?p te0, regardless of the pin is configured as an i nput or an output. (see 14.8 port options .) pte4 pin functions as an external interrupt when pt e4ie=1 in the irq option control regi ster (iocr) and usben=0 in the usb address register (usb disabled). (see 15.9 irq option control register .) d? and d+ ? usb data pins d? and d+ are the differential data lines used by the usb module. (see section 11. uni versal serial bus module (usb) .) the usb module enable bit, usben, in the usb address register (uaddr) controls the pin options for pte4/d ? and pte3/d+. when the usb module is en abled, pte4/d? and pte3/d+ function as usb data pins d? and d+. when the usb module is disabled, pte4/d? and pte3/d+ function as 10ma open-dr ain high current pins for ps/2 clock and data use. the pullup enable bit, pullen, in the usb control register 3 (ucr3) enables a 1.5k ? pullup on d? pin when t he usb module is enabled. (see 11.8.8 usb contro l register 3 .) note: pte4/d? pin has two programmable pul lup resistors. one is used for pte4 when the usb module is di sabled and another is used for d? when the usb m odule is enabled. t2ch01 and t1ch01 ? ti mer channel i/o bits the pte2/t2ch01 and pte1 /t1ch01 pins are th e respective tim2 and tim1 input capture/ output compare pins. th e edge/level select bits, elsxb and elsxa, determine whether the pte2/t2ch01 and pte1/t1ch01 pins are timer channel i/o pins or g eneral-purpose i/o pins. (see section 10. timer interface module (tim) .) tclk ? timer clock input the pte0/tclk pin is the external clock input for tim1 and tim2. the prescaler select bits, ps[2:0 ], select pte0/tclk as the tim clock input. when not selected as the tim cl ock, pte0/tclk is available for general purpose i/o. (see section 10. timer interface module (tim) .) input/output (i/o) ports port e MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 271 note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. however, the ddre bits always determine whether reading port e return s the states of the latches or the stat es of the pins. 14.7.2 data direction register e data direction register e determine s whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables t he output buffer for the corresponding port e pin; a logi c 0 disables the output buffer. ddre[4:0] ? data dire ction register e bits these read/write bits control port e data direction. reset clears ddre[4:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction regist er e bits fr om 0 to 1. figure 14-16 shows the port e i/o circuit logic. address: $0009 bit 7654321bit 0 read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 = unimplemented figure 14-15. data direct ion register e (ddre) input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 272 input/output (i/o) ports freescale semiconductor figure 14-16. port e i/o circuit when bit ddrex is a l ogic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-4 summarizes the operation of the port e pins. 14.8 port options all pins of port a, port b, port c, and port e have programmable pullup resistors. port d has programmabl e led drive capabi lity; ptd5?ptd2 each have 10ma high curr ent sink, and ptd1?ptd 0 each have 25ma high current sink. table 14-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddre[4:0] pin pte[4:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddre[4:0] pte[4:0] pte[4:0] read ddre ($0009) write ddre ($0009) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus input/output (i/o) ports port options MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 273 14.8.1 port option control register the port option control regi ster controls the pullu p options for port a, port b, port c, and port e pins. it also controls t he drive configuration on port d. pte20p ? pins pte[2:0] pullup enable this read/write bit controls the pu llup option for the pte2?pte0 pins, regardless whether the pins are configured as input or output. 1 = configure pte2?pte0 to have internal pullups 0 = disconnect pte2?pte0 internal pullups ptdldd ? led direct drive control this read/write bit c ontrols the output cu rrent capability of ptd5?ptd2 pins. when set, each por t pin has 10ma current sink limit. an led can be connected directly between the pin and v dd without the need of a series resistor. 1 = ptd5?ptd2 conf igured for direct led drive capability; when a pin is set as an output, the pin is an o pen-drain pin with 10ma current sink limit 0 = ptd5?ptd2 configured as standard i/o port pins ptdildd ? infrared led drive control this read/write bit controls the output current capability of ptd1 and ptd0 pins. when set, each port pin has 25ma current sink capability. an infrared led can be connected directly between the pin and v dd . 1 = ptd1 and ptd0 configured fo r infrared led drive capability; when a pin is set as an output, the pin is an o pen-drain pin with 25ma current sink capability 0 = ptd1 and ptd0 configur ed as standard i/o port pins address: $001d bit 7654321bit 0 read: pte20p ptdldd ptdildd pte4p pte3p pcp pbp pap write: reset:00000000 figure 14-17. port option control register (pocr) input/output (i/o) ports technical data MC68HC908JG16 ? rev. 1.1 274 input/output (i/o) ports freescale semiconductor pte4p ? pin pte4 pullup enable this read/write bit contro ls the pullup option for the pte4 pin when the pin is configured as an input a nd the usb module is disabled. 1 = configure pte4 to have internal pullup 0 = disconnect pte4 internal pullup note: when the usb module is enabled, th e pullup controlled by pte4p is disconnected; pte4/d? pin func tions as d? which has a 1.5k ? programmable pull- up resistor. (see 11.8.8 usb contro l register 3 .) pte3p ? pin pte3 pullup enable this read/write bit contro ls the pullup option for the pte3 pin when the pin is configured as an input a nd the usb module is disabled. 1 = configure pte3 to have internal pullup 0 = disconnect pte3 internal pullup pcp ? port c pullup enable this read/write bit controls the pullup option for the ptc1 and ptc0 pins. when set, a pullup device is connected when a pin is configured as an input. 1 = configure port c to have internal pullups 0 = disconnect port c internal pullups pbp ? port b pullup enable this read/write bit cont rols the pullup option fo r ptb0 pin. when set, a pullup device is connected when pt b0 is configured as an input. 1 = disconnect ptb0 internal pullup 0 = configure ptb0 to have internal pullup pap ? port a pullup enable this read/write bit controls the pu llup option for the pta7?pta0 pins. when set, a pullup device is connec ted when a pin is configured as an input. 1 = configure port a to have internal pullups 0 = disconnect port a internal pullups MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 275 technical data ? MC68HC908JG16 section 15. external interrupt (irq) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 15.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 15.6 pte4/d? pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 15.7 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 279 15.8 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 280 15.9 irq option control regist er. . . . . . . . . . . . . . . . . . . . . . . . . . 281 15.2 introduction the irq module provides tw o external interrupt inputs: one dedicated irq pin and one shared port pin, pte4/d?. 15.3 features features of the irq module include: two external interrupt pins, irq and pte4/d? irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge low leakage irq pin for external rc wake up input selectable internal pullup resistor external interrupt (irq) technical data MC68HC908JG16 ? rev. 1.1 276 external interrupt (irq) freescale semiconductor 15.4 functional description a logic 0 applied to the ex ternal interrupt pin ca n latch a cpu interrupt request. figure 15-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clea r the interrupt latch by writing to the acknowledge bit in the inte rrupt status and control register (iscr). writing a logi c 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falling-edge or low-level-triggered. the mode bit in the iscr controls the tr iggering sensitivity of the irq pin. when the interrupt pin is edge-trigger ed only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the cpu interrupt request remains set unt il both of the following occur: vector fetch or software clear return of the interr upt pin to logic one the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. a reset will clear the la tch and the mode control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask bi t in the iscr mask all external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear. note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including ex ternal interrupt requests. (see 8.6 exception control .) external interrupt (irq) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 277 figure 15-1. irq module block diagram addr. register name bit 7 6 5 4 3 2 1 bit 0 $001c irq option control register (iocr) read: 0 0 0 0 0 pte4if pte4ie irqpd write: reset:00000000 $001e irq status and control register (iscr) read: 0 0 0 0 irqf 0 imask mode write: ack reset:00000000 = unimplemented figure 15-2. irq i/o register summary ack imask dq ck clr irq high interrupt to mode select logic irq ff request "1" mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device dq ck clr "1" pte4if pte4ie pte4 irq irqpd read iocr to pte4 pullup enable circuitry external interrupt (irq) technical data MC68HC908JG16 ? rev. 1.1 278 external interrupt (irq) freescale semiconductor 15.5 irq pin the irq pin has a low leakage for input voltages ranging from 0v to v dd ; suitable for applications using rc discharge circuitry to wake up the mcu. a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode bit is set, the irq pin is both falling- edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge si gnal by writing a logic 1 to the ack bit in the inte rrupt status and contro l register (iscr). the ack bit is useful in applic ations that poll the irq pin and require software to clear the irq latch. writing to the ac k bit prior to leaving an interrupt service rout ine can also prevent spurious interrupts due to noise. setting ack does not af fect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bi t latches another interrupt request. if t he irq mask bit, imask, is clear, the cpu loads the progr am counter with the vector address at lo cations $fff 8 and $fff9. return of the irq pin to logic one ? as long as the irq pin is at logic zero, irq remains active. the vector fetch or software cl ear and the return of the irq pin to logic one may occur in any or der. the interrupt reques t remains pending as long as the irq pin is at logic zero. a rese t will clear the latch and the mode control bit, thereby clearing the interrupt ev en if the pin stays low. if the mode bit is clear, the irq pin is falling-edge- sensitive only. with mode clear, a vector fetc h or software clear im mediately clears the irq latch. the irqf bit in the i scr register can be us ed to check for pending interrupts. the irqf bit is not affect ed by the imask bit, which makes it useful in applications wh ere polling is preferred. external interrupt (irq) pte4/d? pin MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 279 use the bih or bil in struction to read the logic level on the irq pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. an internal pullup resistor to v dd is connected to irq pin; this can be disabled by setting the irqpd bit in the irq option control register ($001c). 15.6 pte4/d? pin the pte4 pin is configured as an in terrupt input to trigger the irq interrupt when the followi ng conditions ar e satisfied: the usb module is di sabled (usben = 0) pte4 pin configured for external interrupt input (pte4ie = 1) setting pte4ie configures the pte4 pi n to an input pin with an internal pullup device. the pte4 interrup t is "ored" with the irq input to trigger the irq interrupt (see figure 15-1 . irq m odule block diagram ). therefore, the irq status and contro l register affects both the irq pin and the pte4 pin. an interrupt on pte4 also sets the pte4 interrupt flag, pte4if, in the irq option control register (iocr). 15.7 irq module during break interrupts the system integration module (sim) co ntrols whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 8. system in tegration module (sim) .) to allow software to clear the irq la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared dur ing the break state, it remains cleared when the m cu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writi ng to the ack bit in the irq status and control regi ster during the break state has no effect on the irq latch. external interrupt (irq) technical data MC68HC908JG16 ? rev. 1.1 280 external interrupt (irq) freescale semiconductor 15.8 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq m odule. the iscr has the following functions: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering se nsitivity of the irq pin. irqf ? irq flag this read-only status bi t is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interr upt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/lev el select bit this read/write bit cont rols the triggering se nsitivity of the irq pin. reset clears mode. 1 = irq pin interrupt requests on falling edges and low levels 0 = irq pin interrupt requests on falling edges only address: $001e bit 7654321bit 0 read: 0000irqf0 imask mode write: ack reset: 00000000 = unimplemented figure 15-3. irq status and control register (iscr) external interrupt (irq) irq option control register MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 281 15.9 irq option control register the irq option control r egister controls and mo nitors the external interrupt function availabl e on the pte4 pin. it al so disables/enables the pullup resistor on the irq pin. controls pullup option on irq pin enables pte4 pin for exte rnal interrupts to irq shows the state of t he pte4 interrupt flag pte4if ? pte4 interrupt flag this read-only status bi t is high when a falli ng edge on pte4 pin is detected. pte4if bit clear s when the iocr is read. 1 = falling edge on pte4 is detected and pte4ie is set 0 = falling edge on pte4 is not detected or pte4ie is clear pte4ie ? pte4 interrupt enable this read/write bit enables or disables the in terrupt function on the pte4 pin to trigger the irq inte rrupt. setting the pte4ie bit and clearing the usben bit in the usb address regi ster configure the pte4 pin for interrupt function to the irq interrupt. setting pte4ie also enables the inter nal pullup on pte4 pin. 1 = pte4 interrupt enabled; triggers irq interrupt 0 = pte4 interrupt disabled irqpd ? irq pullup disable this read/write bit c ontrols the pullup option for the irq pin. 1 = internal pull up is disconnected 0 = internal pull-up is connec ted between irq pin and v dd address: $001c bit 7654321bit 0 read: 00000pte4if pte4ie irqpd write: reset: 00000000 = unimplemented figure 15-4. irq option control register (iocr) external interrupt (irq) technical data MC68HC908JG16 ? rev. 1.1 282 external interrupt (irq) freescale semiconductor MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 283 technical data ? MC68HC908JG16 section 16. keyboard interrupt module (kbi) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 16.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16.7.1 keyboard status and control register. . . . . . . . . . . . . . . . 288 16.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 289 16.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 16.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 16.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 16.9 keyboard module during break interrupts . . . . . . . . . . . . . . . 290 16.2 introduction the keyboard interrupt module (kbi ) provides eight independently maskable external interrupts whic h are accessible via pta0?pta7 pins. keyboard interrupt module (kbi) technical data MC68HC908JG16 ? rev. 1.1 284 keyboard interrupt module (kbi) freescale semiconductor 16.3 features features of the keyboard interrupt module include: eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyb oard interrupt mask hysteresis buffers programmable edge-only or edge- and level-interrupt sensitivity exit from low-power modes 16.4 pin name conventions the kbi share eight i/o pins with eight port a i/o pins. the full name of the i/o pins are listed in table 16-1 . the generic pin name appear in the text that follows. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0016 keyboard status and control register (kbscr) read: 0 0 0 0 keyf 0 imaskk modek write: ackk reset:00000000 $0017 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 16-1. i/o r egister summary table 16-1. pin name conventions full mcu pin name kbi generic pin name pin selected for kbi function by kbiex bit in kbier pta7/kba7?pta0/kba0 kba7?kba0 kbie7?kbie0 keyboard interrupt module (kbi) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 285 16.5 functional description figure 16-2. keyboard module block diagram writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin al so enables its internal pullup device. a logic 0 applied to an enabled keyboar d interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low.to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins ar e both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: kbie0 kbie7 . . . dq ck clr v reg modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kba7 kba0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable keyboard interrupt module (kbi) technical data MC68HC908JG16 ? rev. 1.1 286 keyboard interrupt module (kbi) freescale semiconductor vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he ackk bit in the keyboa rd status and control register (kbscr). the a ckk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask k, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the key board interrupt pin is falling-edge- sensitive only. with mo dek clear, a vector fetc h or software clear immediately clears the ke yboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the ke yboard status and control register can be used to see if a pending inte rrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications wh ere polling is preferred. to determine the logi c level on a keyboard inte rrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an inpu t, overriding t he data direction register. however, the dat a direction register bi t must be a logic 0 for software to read the pin. keyboard interrupt module (kbi) keyboard initialization MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 287 16.6 keyboard initialization when a keyboard interrupt pin is enab led, it takes time for the pullup device to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. another way to avoi d a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in data di rection register a. 2. write logic 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 16.7 i/o registers these registers control a nd monitor operation of the keyboard module: keyboard status and cont rol register (kbscr) keyboard interrupt enabl e register (kbier) keyboard interrupt module (kbi) technical data MC68HC908JG16 ? rev. 1.1 288 keyboard interrupt module (kbi) freescale semiconductor 16.7.1 keyboard status and control register flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity keyf ? keyboard flag bit this read-only bit is set when a ke yboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. rese t clears ackk. imaskk ? keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from gene rating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard tri ggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $0016 bit 7654321bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 16-3. keyboard status and control regi ster (kbscr) keyboard interrupt module (kbi) low-power modes MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 289 16.7.2 keyboard interrupt enable register the keyboard interrupt enabl e register enables or disables each port a pin to operate as a ke yboard interrupt pin. kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax/kbax pin enabled as keyboard interrupt pin 0 = ptax/kbax not enabled as keyboard interrupt pin 16.8 low-power modes the wait and stop in structions put the mcu in low-power consumption standby modes. 16.8.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to brin g the mcu out of wait mode. 16.8.2 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to bring the mcu out of stop mode. address: $0017 bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 16-4. keyboard interr upt enable register (kbier) keyboard interrupt module (kbi) technical data MC68HC908JG16 ? rev. 1.1 290 keyboard interrupt module (kbi) freescale semiconductor 16.9 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during t he break state. the bcfe bit in the break flag control register (bfcr) enabl es software to clear status bits during the break state. to allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared w hen the mcu exits the break state. to protect the latch during the break st ate, write a logi c 0 to the bcfe bit. with bcfe at logi c 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break stat e has no effect. (see 16.7.1 keyboard status and control register .) MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 291 technical data ? MC68HC908JG16 section 17. computer operating properly (cop) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 17.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.1 oscdclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 17.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 17.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 17.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 294 17.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 17.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 17.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 17.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 17.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 17.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 17.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 296 17.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config register. computer operating properly (cop) technical data MC68HC908JG16 ? rev. 1.1 292 computer operating properly (cop) freescale semiconductor 17.3 functional description figure 17-1 shows the structure of the cop module. figure 17-1. cop block diagram the cop counter is a free-running 6- bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchr onous reset after 2 18 ?2 4 or 2 13 ?2 4 oscdclk cycles, depending on the state of the co p rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 oscdclk cycle overflow option, a 24 mhz oscdclk (12mhz crystal) gives a cop timeout period of 10.92m s. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the prescaler. note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. copctl write oscdclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config) cop rate sel (coprs from config) clear stages 5?12 computer operating properly (cop) i/o signals MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 293 a cop reset pulls the rst pin low for 32 oscdcl k cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst . during the br eak state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 17.4 i/o signals the following paragraphs descri be the signals shown in figure 17-1 . 17.4.1 oscdclk oscdclk is the crystal oscillator clock doubler output signal. its frequency is two times the crystal frequency. 17.4.2 stop instruction the stop instruction cl ears the cop prescaler. 17.4.3 copctl write writing any value to the cop c ontrol register (copctl) (see 17.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the prescaler. reading the cop cont rol register retu rns the low byte of the reset vector. 17.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 oscdclk cycles after power-up. computer operating properly (cop) technical data MC68HC908JG16 ? rev. 1.1 294 computer operating properly (cop) freescale semiconductor 17.4.5 internal reset an internal reset clears the co p prescaler and the cop counter. 17.4.6 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the cop prescaler. 17.4.7 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the config register. (see figure 17-2 .) 17.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the config register. (see figure 17-2 .) coprs ? cop rate select bit coprs selects the cop timeout period. rese t clears coprs. 1 = cop timeout period is 2 13 ? 2 4 oscdclk cycles 0 = cop timeout period is 2 18 ? 2 4 oscdclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: lvidr lvi5or3 urstd lvid ssrec coprs stop copd write: reset:0*0*0*0*0000 * lvidr, lvi5or3, urstd, and lvid, are reset by por or lvi reset only. figure 17-2. configurat ion register (config) computer operating properly (cop) cop control register MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 295 17.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 17.6 interrupts the cop does not generate cpu interrupt requests. 17.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is enter ed by having blank rese t vectors and not having v tst on the irq pin, the cop is automatic ally disabled until a por occurs. 17.8 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clears cop counter (any value) reset: unaffected by reset figure 17-3. cop cont rol register (copctl) computer operating properly (cop) technical data MC68HC908JG16 ? rev. 1.1 296 computer operating properly (cop) freescale semiconductor 17.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodi cally clear the cop counter in a cpu interrupt routine. 17.8.2 stop mode stop mode turns off the oscdclk input to the cop and clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. to prevent inadvertently turning off t he cop with a stop instruction, a configuration option is av ailable that disables the stop instruction. when the stop bit in the config uration register has the stop instruction is disabled, execution of a stop in struction results in an illegal opcode reset. 17.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor low-voltage inhibit (lvi) 297 technical data ? MC68HC908JG16 section 18. low-voltage inhibit (lvi) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 18.4.1 low v dd detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 18.4.2 low v reg detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 18.5 lvi control and configur ation . . . . . . . . . . . . . . . . . . . . . . . . 299 18.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 18.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.2 introduction this section describes the low-vo ltage inhibit (lvi) module, which monitors the voltage on the v dd pin and v reg pin. and can force a reset when the v dd or v reg voltage falls below the lvi trip falling voltage. 18.3 features features of the lvi module include: independent voltage monito ring circuits for v dd and v reg independent lvi circ uit disable for v dd and v reg selectable lvi trip voltage for v dd low-voltage inhibit (lvi) technical data MC68HC908JG16 ? rev. 1.1 298 low-voltage inhibit (lvi) freescale semiconductor figure 18-1. lvi module block diagram 18.4 functional description figure 18-1 shows the structur e of the lvi module. the lvi is enabled out of reset. the lvi module c ontains independent bandgap reference circuit and comparator for monitoring the v dd voltage and the v reg voltage. an lvi reset perf orms a mcu internal reset and drives the rst pin low to provide low-vo ltage protection to exte rnal peripheral devices. 18.4.1 low v dd detector the low v dd detector circuit monitors the v dd voltage and forces a lvi reset when the v dd voltage falls below the tri p voltage. the lvi5or3 bit in the configuration regi ster (config) selects t he trip point voltage. the v dd lvi circuit can be dis abled by the setting the lvid bit in config. see 8.4.2.5 low-voltage in hibit (lvi) reset for details of the interaction between th e sim and the lvi. low v dd lv i d detector v dd lvi reset v dd > v lvr = 0 v dd < v lvr = 1 low v reg lv i d r detector v reg v dd > v lvrr = 0 v dd < v lvrr = 1 lv i 5 o r 3 low-voltage inhibit (lvi) lvi control and configuration MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor low-voltage inhibit (lvi) 299 18.4.2 low v reg detector the low v reg detector circuit monitors the v reg voltage and forces a lvi reset when the v reg voltage falls below th e trip voltage. the v reg lvi circuit can be disabl ed by the setting the lvidr bit in config. note: there is no lvi circuit for v rega . 18.5 lvi control and configuration three bits in the configuration regi ster (config) c ontrol the operation of the lvi module. lvidr ? lvi disable bit for v reg lvidr disables the lvi circuit for v reg . 1 = lvi circuit for v reg disabled 0 = lvi circuit for v reg enabled lvi5or3 ? lvi trip point voltage select bit for v dd lvi5or3 selects the trip point vo ltage of the lvi circuit for v dd . see section 20. electrical specifications for the trip vo ltage tolerances. 1 = lvi trips at 3.3v 0 = lvi trips at 2.4v lvid ? lvi dis able bit for v dd lvid disables the lvi circuit for v dd . 1 = lvi circuit for v dd disabled 0 = lvi circuit for v dd enabled address: $001f bit 7654321bit 0 read: lvidr lvi5or3 urstd lvid ssrec coprs stop copd write: reset: 0* 0* 0* 0* 0 0 0 0 = unimplemented * lvidr, lvi5or3, urstd, and lvid bits are rese t by por (power-on reset) or lvi reset only. figure 18-2. configura tion register (config) low-voltage inhibit (lvi) technical data MC68HC908JG16 ? rev. 1.1 300 low-voltage inhibit (lvi) freescale semiconductor 18.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 18.6.1 wait mode if enabled, the lvi module rema ins active in wait mode. 18.6.2 stop mode if enabled, the lvi module rema ins active in stop mode. MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor break module (brk) 301 technical data ? MC68HC908JG16 section 19. break module (brk) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 19.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 304 19.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .304 19.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 304 19.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 304 19.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 19.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 19.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 19.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 19.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 305 19.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 306 19.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 308 19.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. break module (brk) technical data MC68HC908JG16 ? rev. 1.1 302 break module (brk) freescale semiconductor 19.3 features features of the br eak module include: accessible input/output (i/o) regi sters during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 19.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal to the cpu. the cpu then loads the instruct ion register with a software interrupt instruction (swi) afte r completion of the current cpu instruction. the program count er vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return-from-inter rupt instruction (r ti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 19-1 shows the structure of the break module. break module (brk) functional description MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor break module (brk) 303 figure 19-1. break module block diagram iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 19-2. break modul e i/o register summary break module (brk) technical data MC68HC908JG16 ? rev. 1.1 304 break module (brk) freescale semiconductor 19.4.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bi ts during the break state. 19.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program count er with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 19.4.3 tim during break interrupts a break interrupt stops the timer counters. 19.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 19.5 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 19.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see section 8. system in tegration module (sim) ). clear the sbsw bit by writi ng logic 0 to it. break module (brk) break module registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor break module (brk) 305 19.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 19.6 break module registers these registers control and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) sim break status register (sbsr) sim break flag con trol register (sbfcr) 19.6.1 break status and control register the break status and control register (brkscr) contai ns break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16 -bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 19-3. break status an d control register (brkscr) break module (brk) technical data MC68HC908JG16 ? rev. 1.1 306 break module (brk) freescale semiconductor brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) br eak address match 0 = (when read) no break address match 19.6.2 break address registers the break address register s (brkh and brkl) contai n the high and low bytes of the desired brea kpoint address. reset clears the break address registers. 19.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode a fter exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 19-4. break addres s register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 19-5. break addr ess register low (brkl) break module (brk) break module registers MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor break module (brk) 307 sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r=reserved figure 19-6. sim break stat us register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. break module (brk) technical data MC68HC908JG16 ? rev. 1.1 308 break module (brk) freescale semiconductor 19.6.4 sim break flag control register the sim break flag control register (s bfcr) contains a bit that enables software to clear status bits wh ile the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to cl ear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r=reserved figure 19-7. sim break flag c ontrol register (sbfcr) MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor electrical specifications 309 technical data ? MC68HC908JG16 section 20. electrical specifications 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 20.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 310 20.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 311 20.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 20.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 312 20.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 20.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 20.9 timer interface module characterist ics . . . . . . . . . . . . . . . . . 314 20.10 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 314 20.11 usb low-speed source electrical characteri stics . . . . . . . . 315 20.12 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.13 adc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . 317 20.14 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 318 electrical specifications technical data MC68HC908JG16 ? rev. 1.1 310 electrical specifications freescale semiconductor 20.2 introduction this section contains electrical and timing specifications. 20.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 20.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) notes : 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage pte4/d?, pte3/d+ others v in v ss ? 1.0 to v dd +0.3 v ss ? 0.3 to v dd +0.3 v mode entry voltage, irq pin v tst v ss ?0.3 to +8 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss /v ss i mvss 100 ma maximum current into v dd /v dda i mvdd 100 ma electrical specifications functional operating range MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor electrical specifications 311 20.4 functional operating range 20.5 thermal characteristics characteristic symbol value unit operating temperature range t a 0 to 70 c operating voltage range v dd 4.0 to 5.5 v characteristic symbol value unit thermal resistance lqfp (32 pins) ja 95 c/w i/o pin power dissipation p i/o user-determined w power dissipation (1) notes : 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + (i dda v dda ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measure p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c ) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 100 c electrical specifications technical data MC68HC908JG16 ? rev. 1.1 312 electrical specifications freescale semiconductor 20.6 dc electrical characteristics characteristic (1) symbol min typ (2) max unit regulator output voltage v reg v rega 3.0 2.9 3.3 3.3 3.6 3.7 v output high voltage (i load = ?2.0 ma) pta0?pta7, ptb0, ptc0?ptc1, pte0?pte2 v oh v dd ?0.8 ??v output low voltage (i load = 1.6 ma) all i/o pins (i load = 25 ma) ptd0?ptd1 in ildd mode (i load = 10 ma) pte3?pte4 with usb is disabled v ol ? ? ? ? ? ? 0.4 0.5 0.4 v input high voltage osc1 all ports, irq , rst v ih 0.7 v reg 0.7 v dd ? ? v reg v dd v input low voltage osc1 all ports, irq , rst v il v ss v ss ? ? 0.3 v reg 0.3 v dd v output low current (v ol = 2.0 v) ptd2?ptd5 in ldd mode i ol 10 13 20 ma v dd supply current, v dd = 5.25v, f op = 6mhz run, with low speed usb (3) run, with usb suspended (3) wait, with low speed usb (4) wait, with usb suspended (4) stop (0 c to 70 c) (5) i dd ? ? ? ? ? 7.0 6.5 3.0 2.5 60 8.5 8.0 5.0 4.0 100 ma ma ma ma a i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) v por 0?100mv por rise-time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 8 v pullup resistors port a, ptb0, port c, pte0?pte2, rst , irq (to v dd ) pte3?pte4 with usb module disabled (to v dd ) d? with usb module enabled (to v reg ) r pu 20 4 1.1 35 5 1.5 50 6 2.0 k ? v dd lvi trip point vo ltage (lvi5or3 = 0) v lvr 2.0 2.4 2.8 v v dd lvi trip point vo ltage (lvi5or3 = 1) 2.8 3.3 3.8 v reg lvi trip point voltage 2.0 2.2 2.6 electrical specifications control timing MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor electrical specifications 313 20.7 control timing 20.8 oscillator characteristics notes : 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f xclk = 12mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f xclk = 12mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; 15 k ? 5% termination resistors on d+ and d? pins; all ports configured as inputs; osc2 capacitance linearly affects wait i dd 5. stop i dd measured with usb in suspend mode; osc1 grounded; no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the inter nal por reset is released, rst must be driven low externally until minimum v dd is reached. characteristic (1) notes : 1. v dd = 4.0 to 5.5 vdc; v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. f op ?6mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 125 ? ns characteristic symbol min typ max unit crystal frequency (1) notes : 1. the usb module is de signed to operate with f xclk = 12 mhz. f xclk 112 12 mhz external clock reference frequency (1), (2) 2. no more than 10% duty cycle deviation from 50%. f xclk dc 12 12 mhz crystal load capacitance (3) 3. consult crystal vendor data sheet. c l ?? ? crystal fixed capacitance (3) c 1 ? 2 c l ? crystal tuning capacitance (3) c 2 ? 2 c l ? feedback bias resistor r b ?10 m ? ? series resistor (3), (4) 4. not required for high-frequency crystals. r s ?? ? electrical specifications technical data MC68HC908JG16 ? rev. 1.1 314 electrical specifications freescale semiconductor 20.9 timer interface module characteristics 20.10 usb dc electrical characteristics characteristic symbol min max unit input capture pulse width t tih, t til 1/f op ?ns input clock pulse width t tch, t tcl (1/f op ) + 5 ?ns characteristic (1) notes : 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol conditions min typ max unit hi-z state data line leakage i lo 0 v electrical specifications technical data MC68HC908JG16 ? rev. 1.1 316 electrical specifications freescale semiconductor 20.12 usb signaling levels bus state signaling levels transmit receive differential 1 d+ > v oh (min) and d? < v ol (max) (d+) ? (d?) > 200 mv differential 0 d? > v oh (min) and d? < v ol (max) (d?) ? (d+) > 200 mv single-ended 0 (se0) d+ and d? < v ol (max) d+ and d? < v il (max) data j state (low speed) dif ferential 0 differential 0 data k state (low speed) differential 1 differential 1 idle state (low speed) na d? > v ihz (min) and d+ < v il (max) resume state differential 1 differential 1 start of packet (sop) data lines switch from idle to k state end of packet (eop) se0 for approximately 2 bit times (1) followed by a j state for 1 bit time notes : 1. the width of eop is defined in bit time s relative to the speed of transmission. se0 for 1 bit time (2) followed by a j state for 1 bit time 2. the width of eop is defined in bit times relative to the device type receiving the eop. the bit time is approximate. reset na d+ and d? < v il (max) for 8 s electrical specifications adc electrical characteristics MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor electrical specifications 317 20.13 adc electrical characteristics characteristic (1) notes : 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min max unit comments supply voltage v dda 4.0 5.5 v v dda should be tied to the same potential as v dd via separate traces. adc reference voltage high v refh ? v rega v adc reference voltage low v refl v ssa ?v input voltages v adin v refl v refh v resolution b ad 88bits absolute accuracy a ad ? 1 lsb includes quantization adc internal clock f adic 0.75 1.572 mhz t aic = 1/f adic , tested only at 1.5mhz conversion range r ad v refl v refh v power-up time t adpu 16 ? t aic cycles conversion time t adc 16 17 t aic cycles sample time (2) 2. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. t ads 5? t aic cycles zero input reading (3) 3. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. z adi 00 01 hex full-scale reading (3) f adi fe ff hex input capacitance c adi ? 8 pf not tested input leakage (4) port a 4. the external system error caused by input leakage current is approximately equal to the product of r source and input current. ?? 1 a electrical specifications technical data MC68HC908JG16 ? rev. 1.1 318 electrical specifications freescale semiconductor 20.14 flash memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v flash block size ? 512 bytes flash programming size ? 64 bytes flash read bus clock frequency f read (1) notes : 1. f read is defined as the frequency range for which the flash memory can be read. 32 k 8.4 m hz flash block erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, bu t it reduced the endurance of the flash memory. 10 ? ms flash mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, bu t it reduces the endurance of the flash memory. 200 ? ms flash pgm/erase to hven set up time t nvs 5? s flash high-voltage hold time t nvh 5? s flash high-voltage hold time (mass erase) t nvhl 100 ? s flash program hold time t pgs 10 ? s flash program time t prog 20 40 s flash return to read time t rcv (4) 4. t rcv is defined as the time it n eeds before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1? s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. ?8ms flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ?10k?cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ?10k?cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ?10?years MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor mechanical specifications 319 technical data ? MC68HC908JG16 section 21. mechanical specifications 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 21.3 32-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 320 21.2 introduction this section gives t he dimensions for: 32-pin low-profile qu ad flat pack (case #873a) mechanical specifications technical data MC68HC908JG16 ? rev. 1.1 320 mechanical specifications freescale semiconductor 21.3 32-pin low-profile quad flat pack (lqfp) figure 21-1. 32-pi n lqfp (case #873a) w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 ?t? ?z? ?u? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t?u m 0.20 (0.008) z ac MC68HC908JG16 ? rev. 1.1 technical data freescale semiconductor ordering information 321 technical data ? MC68HC908JG16 section 22. ordering information 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 22.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 22.2 introduction this section contains ordering numbers for the MC68HC908JG16. 22.3 mc order numbers table 22-1. mc order numbers mc order number package operating temperature range MC68HC908JG16fa 32-pin lqfp 0 to +70 c ordering information technical data MC68HC908JG16 ? rev. 1.1 322 ordering information freescale semiconductor how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 1.1 MC68HC908JG16/d august 16, 2005 |
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